Constrained worst case loads for microprocessors

W. J. Lambert, Raja Ayyanar

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The risk of a microprocessor execution error increases as the voltage at the die decreases, making worst case analysis of the die voltage a good metric for microprocessor voltage regulation performance. However, the actual worst case load is unlikely to ever occur. This paper derives the results for the worst case load from linear system theory, and then uses a constrained optimization problem to calculate the worst case load under more probable circumstances, demonstrating that loads with much higher likelihood of occurrence can cause voltages at the die nearly as low as the worst case.

Original languageEnglish (US)
Title of host publication2008 23rd Annual IEEE Applied Power Electronics Conference and Exposition, APEC
Pages1061-1066
Number of pages6
DOIs
StatePublished - Aug 18 2008
Event2008 23rd Annual IEEE Applied Power Electronics Conference and Exposition, APEC - Austin, TX, United States
Duration: Feb 24 2008Feb 28 2008

Publication series

NameConference Proceedings - IEEE Applied Power Electronics Conference and Exposition - APEC

Other

Other2008 23rd Annual IEEE Applied Power Electronics Conference and Exposition, APEC
CountryUnited States
CityAustin, TX
Period2/24/082/28/08

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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