Computation of joint timing yield of sequential networks considering process variations

Amit Goel, Sarvesh Bhardwaj, Praveen Ghanta, Sarma Vrudhula

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

This paper presents a framework for estimating the timing yield of sequential networks in the presence of process variations. We present an accurate method for characterizing various parameters such as setup time, hold time, clock to output delay etc. of sequential elements in the network. Using these models and the models of interconnects gate delays, and clock skews, we perform statistical timing analysis of combinational blocks in the circuit. The result of the timing analysis is a set of constraints involving random process variables that the network has to satisfy together in order to work correctly. We compute the joint yield of all the constraints to estimate the yield of the entire network. The proposed method provides a speedup of up to 400 × compared to 10000 Monte Carlo simulations with an average error of less than 1% and 5% in mean and standard deviation respectively.

Original languageEnglish (US)
Title of host publicationIntegrated Circuit and System Design
Subtitle of host publicationPower and Timing Modeling, Optimization and Simulation - 17th International Workshop, PATMOS 2007, Proceedings
Pages125-137
Number of pages13
StatePublished - Dec 1 2007
Event17th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2007 - Gothenburg, Sweden
Duration: Sep 3 2007Sep 5 2007

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume4644 LNCS
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349

Other

Other17th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2007
CountrySweden
CityGothenburg
Period9/3/079/5/07

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ASJC Scopus subject areas

  • Theoretical Computer Science
  • Computer Science(all)

Cite this

Goel, A., Bhardwaj, S., Ghanta, P., & Vrudhula, S. (2007). Computation of joint timing yield of sequential networks considering process variations. In Integrated Circuit and System Design: Power and Timing Modeling, Optimization and Simulation - 17th International Workshop, PATMOS 2007, Proceedings (pp. 125-137). (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 4644 LNCS).