Complete logic family using tunneling-phase-logic devices

H. A.H. Fahmy, R. A. Kiehl

Research output: Chapter in Book/Report/Conference proceedingConference contribution

29 Scopus citations

Abstract

This paper presents the work done to develop and characterize the behavior of binary tunneling phase logic (TPL) devices. Three input NAND, NOR and MINORITY functions are demonstrated using a single TPL element. The fan-out of the gates is discussed as well as the loading effects of multiple gates in cascade. Stable regions of operation are reported and future research possibilities are explored.

Original languageEnglish (US)
Title of host publicationICM 1999 - 11th International Conference on Microelectronics
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages153-156
Number of pages4
ISBN (Electronic)0780366433
DOIs
StatePublished - Jan 1 1999
Externally publishedYes
Event11th International Conference on Microelectronics, ICM 1999 - Kuwait City, Kuwait
Duration: Nov 22 1999Nov 24 1999

Publication series

NameProceedings of the International Conference on Microelectronics, ICM
Volume2000-January

Other

Other11th International Conference on Microelectronics, ICM 1999
CountryKuwait
CityKuwait City
Period11/22/9911/24/99

Keywords

  • CMOS logic circuits
  • Capacitance
  • Clocks
  • Digital circuits
  • Electrons
  • Frequency
  • Logic circuits
  • Logic devices
  • Tunneling
  • Voltage

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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  • Cite this

    Fahmy, H. A. H., & Kiehl, R. A. (1999). Complete logic family using tunneling-phase-logic devices. In ICM 1999 - 11th International Conference on Microelectronics (pp. 153-156). [884828] (Proceedings of the International Conference on Microelectronics, ICM; Vol. 2000-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICM.2000.884828