Compilation framework for code size reduction using reduced bit-width ISAs (rISAs)

Aviral Shrivastava, Partha Biswas, Ashok Halambi, Nikil Dutt, Alex Nicolau

Research output: Contribution to journalArticle

11 Scopus citations

Abstract

For many embedded applications, program code size is a critical design factor. One promising approach for reducing code size is to employ a "dual instruction set", where processor architectures support a normal (usually 32-bit) Instruction Set, and a narrow, space-efficient (usually 16-bit) Instruction Set with a limited set of opcodes and access to a limited set of registers. This feature however, requires compilers that can reduce code size by compiling for both Instruction Sets. Existing compiler techniques operate at the routine-level granularity and are unable to make the trade-off between increased register pressure (resulting in more spills) and decreased code size. We present a compilation framework for such dual instruction sets, which uses a profitability based compiler heuristic that operates at the instruction-level granularity and is able to effectively take advantage of both Instruction Sets. We demonstrate consistent and improved code size reduction (on average 22%), for the MIPS 32/16 bit ISA. We also show that the code compression obtained by this "dual instruction set" technique is heavily dependent on the application characteristics and the narrow Instruction Set itself.

Original languageEnglish (US)
Pages (from-to)123-146
Number of pages24
JournalACM Transactions on Design Automation of Electronic Systems
Volume11
Issue number1
Publication statusPublished - 2006
Externally publishedYes

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Keywords

  • Code compression
  • Code generation
  • Codesize reduction
  • Compilers
  • Dual instruction set
  • Narrow bit-width instruction set
  • Optimization
  • Register pressure-based code generation
  • Retargetable compilers
  • rISA
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ASJC Scopus subject areas

  • Hardware and Architecture
  • Computer Graphics and Computer-Aided Design
  • Software

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