Comparison of wet and dry etching of zinc indium oxide for thin film transistors with an inverted gate structure

Michael A. Marrs, Bryan D. Vogt, Gregory Raupp

Research output: Contribution to journalArticle

3 Citations (Scopus)

Abstract

Not only are amorphous oxide semiconductor thin film transistors (TFTs) extremely sensitive to the processing of the active layer, but subsequent layer processing can also impact the performance. Due to this sensitivity, many surface treatments and passivation techniques for the active layer have been developed, but the influence of the etching of the active layer itself has not been explored extensively. These etch steps are especially critical in the manufacture of flexible microelectronics, for which process conditions are inherently limited by thermal stability of the plastic (200 C) and incompatibility of the plastic substrate with highly oxidizing chemical environments. Here, a novel dry etch process is compared to typical wet etch process in the context of flexible zinc indium oxide TFT array fabrication on plastic. The dry etch process provides superior control of the sidewall profile and the etch selectivity. These improvements using a dry etch approach decrease the off current of the TFT by 3 orders of magnitude from 2.65 nA for the wet etch process to 0.71 pA using the dry etch with a concurrent improvement in the device yield to 100 (for 120 transistors) with the dry etch. Additionally, the subthreshold slope improves from 1.9 to 1.0 V/decade, while the saturation mobility (6.5 cm 2/Vs) is not impacted by the etch process.

Original languageEnglish (US)
Article number011505
JournalJournal of Vacuum Science and Technology A: Vacuum, Surfaces and Films
Volume30
Issue number1
DOIs
StatePublished - Jan 2012
Externally publishedYes

Fingerprint

Gates (transistor)
Dry etching
Wet etching
Thin film transistors
zinc oxides
indium oxides
Indium
Zinc
transistors
etching
Plastics
Oxides
plastics
thin films
Amorphous semiconductors
Processing
Passivation
Microelectronics
incompatibility
Oxide films

ASJC Scopus subject areas

  • Condensed Matter Physics
  • Surfaces and Interfaces
  • Surfaces, Coatings and Films

Cite this

@article{91961046da084020ac88b5158106cf2e,
title = "Comparison of wet and dry etching of zinc indium oxide for thin film transistors with an inverted gate structure",
abstract = "Not only are amorphous oxide semiconductor thin film transistors (TFTs) extremely sensitive to the processing of the active layer, but subsequent layer processing can also impact the performance. Due to this sensitivity, many surface treatments and passivation techniques for the active layer have been developed, but the influence of the etching of the active layer itself has not been explored extensively. These etch steps are especially critical in the manufacture of flexible microelectronics, for which process conditions are inherently limited by thermal stability of the plastic (200 C) and incompatibility of the plastic substrate with highly oxidizing chemical environments. Here, a novel dry etch process is compared to typical wet etch process in the context of flexible zinc indium oxide TFT array fabrication on plastic. The dry etch process provides superior control of the sidewall profile and the etch selectivity. These improvements using a dry etch approach decrease the off current of the TFT by 3 orders of magnitude from 2.65 nA for the wet etch process to 0.71 pA using the dry etch with a concurrent improvement in the device yield to 100 (for 120 transistors) with the dry etch. Additionally, the subthreshold slope improves from 1.9 to 1.0 V/decade, while the saturation mobility (6.5 cm 2/Vs) is not impacted by the etch process.",
author = "Marrs, {Michael A.} and Vogt, {Bryan D.} and Gregory Raupp",
year = "2012",
month = "1",
doi = "10.1116/1.3668090",
language = "English (US)",
volume = "30",
journal = "Journal of Vacuum Science and Technology A",
issn = "0734-2101",
publisher = "AVS Science and Technology Society",
number = "1",

}

TY - JOUR

T1 - Comparison of wet and dry etching of zinc indium oxide for thin film transistors with an inverted gate structure

AU - Marrs, Michael A.

AU - Vogt, Bryan D.

AU - Raupp, Gregory

PY - 2012/1

Y1 - 2012/1

N2 - Not only are amorphous oxide semiconductor thin film transistors (TFTs) extremely sensitive to the processing of the active layer, but subsequent layer processing can also impact the performance. Due to this sensitivity, many surface treatments and passivation techniques for the active layer have been developed, but the influence of the etching of the active layer itself has not been explored extensively. These etch steps are especially critical in the manufacture of flexible microelectronics, for which process conditions are inherently limited by thermal stability of the plastic (200 C) and incompatibility of the plastic substrate with highly oxidizing chemical environments. Here, a novel dry etch process is compared to typical wet etch process in the context of flexible zinc indium oxide TFT array fabrication on plastic. The dry etch process provides superior control of the sidewall profile and the etch selectivity. These improvements using a dry etch approach decrease the off current of the TFT by 3 orders of magnitude from 2.65 nA for the wet etch process to 0.71 pA using the dry etch with a concurrent improvement in the device yield to 100 (for 120 transistors) with the dry etch. Additionally, the subthreshold slope improves from 1.9 to 1.0 V/decade, while the saturation mobility (6.5 cm 2/Vs) is not impacted by the etch process.

AB - Not only are amorphous oxide semiconductor thin film transistors (TFTs) extremely sensitive to the processing of the active layer, but subsequent layer processing can also impact the performance. Due to this sensitivity, many surface treatments and passivation techniques for the active layer have been developed, but the influence of the etching of the active layer itself has not been explored extensively. These etch steps are especially critical in the manufacture of flexible microelectronics, for which process conditions are inherently limited by thermal stability of the plastic (200 C) and incompatibility of the plastic substrate with highly oxidizing chemical environments. Here, a novel dry etch process is compared to typical wet etch process in the context of flexible zinc indium oxide TFT array fabrication on plastic. The dry etch process provides superior control of the sidewall profile and the etch selectivity. These improvements using a dry etch approach decrease the off current of the TFT by 3 orders of magnitude from 2.65 nA for the wet etch process to 0.71 pA using the dry etch with a concurrent improvement in the device yield to 100 (for 120 transistors) with the dry etch. Additionally, the subthreshold slope improves from 1.9 to 1.0 V/decade, while the saturation mobility (6.5 cm 2/Vs) is not impacted by the etch process.

UR - http://www.scopus.com/inward/record.url?scp=84855588185&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84855588185&partnerID=8YFLogxK

U2 - 10.1116/1.3668090

DO - 10.1116/1.3668090

M3 - Article

AN - SCOPUS:84855588185

VL - 30

JO - Journal of Vacuum Science and Technology A

JF - Journal of Vacuum Science and Technology A

SN - 0734-2101

IS - 1

M1 - 011505

ER -