Systolic architectures for matrix multiplication are compared in terms of the maximum speedup which can be achieved with increased processor count in a monolithically integrated circuit. The comparison process integrates the architectural characteristics and the technological parameters. The optimum systolic architecture is found for different limiting factors including switching delay, power dissipation, I/O bandwidth, and clock skew. The interplay between limiting factors is studied through the implementation of an inner-product step processor using 3- mu m CMOS technology and its down-scaled version. For a given chip size and technology there is a critical level of heat extraction which separates a power-dissipation-limited case from a switching-delay limited case.
|Original language||English (US)|
|Journal||IEEE Journal of Solid-State Circuits|
|State||Published - Feb 1 1987|
ASJC Scopus subject areas
- Electrical and Electronic Engineering