Neural networks in a variety of configurations have demonstrated the ability to choose rapidly the stored item that most closely matches a given input. A significant drawback to such an approach from an integrated circuit standpoint is the large number of interconnections required between the individual elements. The authors have designed and fabricated a memory device with the above feature that is capable of significant data throughput rates. An overview of the architecture is presented, and its characteristics are compared to that of other neural networks through simulation.
|Original language||English (US)|
|Title of host publication||Unknown Host Publication Title|
|Editors||Maureen Caudill, Charles T. Butler, San Diego Adaptics|
|Place of Publication||San Diego, CA, USA|
|State||Published - 1987|
ASJC Scopus subject areas