Compact modeling of stress effects in scaled CMOS

Chi Chao Wang, Wei Zhao, Frank Liu, Min Chen, Yu Cao

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Scopus citations

Abstract

Strained Si is implemented into the standard CMOS process to enhance carrier transport properties since the 90nm technology node. However, due to the non-uniform stress distribution in the channel, the enhancement of carrier mobility and threshold voltage strongly depend on layout parameters, such as channel length (L) and source/drain diffusion length (Lsd). In this work, a compact model that physically captures these behaviors is developed for circuit simulation with strained CMOS technology.

Original languageEnglish (US)
Title of host publicationSISPAD 2009 - 2009 International Conference on Simulation of Semiconductor Processes and Devices
DOIs
StatePublished - Dec 1 2009
EventSISPAD 2009 - 2009 International Conference on Simulation of Semiconductor Processes and Devices - San Diego, CA, United States
Duration: Sep 9 2009Sep 11 2009

Publication series

NameInternational Conference on Simulation of Semiconductor Processes and Devices, SISPAD

Other

OtherSISPAD 2009 - 2009 International Conference on Simulation of Semiconductor Processes and Devices
CountryUnited States
CitySan Diego, CA
Period9/9/099/11/09

Keywords

  • Compact modeling
  • Layout dependence
  • Mobility
  • Stress effect
  • Threshold voltage

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Computer Science Applications
  • Modeling and Simulation

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  • Cite this

    Wang, C. C., Zhao, W., Liu, F., Chen, M., & Cao, Y. (2009). Compact modeling of stress effects in scaled CMOS. In SISPAD 2009 - 2009 International Conference on Simulation of Semiconductor Processes and Devices [5290231] (International Conference on Simulation of Semiconductor Processes and Devices, SISPAD). https://doi.org/10.1109/SISPAD.2009.5290231