@inproceedings{542286d282074da684408cfd5bfb93ee,
title = "Compact modeling of stress effects in scaled CMOS",
abstract = "Strained Si is implemented into the standard CMOS process to enhance carrier transport properties since the 90nm technology node. However, due to the non-uniform stress distribution in the channel, the enhancement of carrier mobility and threshold voltage strongly depend on layout parameters, such as channel length (L) and source/drain diffusion length (Lsd). In this work, a compact model that physically captures these behaviors is developed for circuit simulation with strained CMOS technology.",
keywords = "Compact modeling, Layout dependence, Mobility, Stress effect, Threshold voltage",
author = "Wang, {Chi Chao} and Wei Zhao and Frank Liu and Min Chen and Yu Cao",
year = "2009",
doi = "10.1109/SISPAD.2009.5290231",
language = "English (US)",
isbn = "9781424439492",
series = "International Conference on Simulation of Semiconductor Processes and Devices, SISPAD",
booktitle = "SISPAD 2009 - 2009 International Conference on Simulation of Semiconductor Processes and Devices",
note = "SISPAD 2009 - 2009 International Conference on Simulation of Semiconductor Processes and Devices ; Conference date: 09-09-2009 Through 11-09-2009",
}