Compact modeling of Fe-FET and implications on variation-insensitive design

Chi Chao Wang, Yun Ye, Yu Cao

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Abstract

Semiconductor devices with self-feedback mechanisms are considered as a promising alternative to traditional CMOS, in order to achieve faster operation and lower switching energy. Examples include IMOS and FBFET that are operated in a non-equilibrium condition to rapidly generate mobile carriers [1-2]. More recently, Fe-FET was proposed to improve the switching by integrating a ferroelectric material as gate insulator in a MOSFET structure [3-5]. Under particular circumstance, ferroelectric capacitance is effectively negative, due to the negative slope of its polarization-electrical field (P-E) curve. This property makes the ferroelectric layer a voltage amplifier to boost surface potential, achieving fast transition. In this paper: (1) A new threshold voltage model is developed to capture the feedback of negative capacitance and IV characteristics of Fe-FET; (2) It is further revealed that the impact of random dopant fluctuation (RDF) on leakage variability can be significantly suppressed in Fe-FET, by tuning the thickness of the ferroelectric layer.

Original languageEnglish (US)
Title of host publicationInternational Conference on Simulation of Semiconductor Processes and Devices, SISPAD
Pages247-250
Number of pages4
DOIs
StatePublished - 2010
Event15th International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2010 - Bologna, Italy
Duration: Sep 6 2010Sep 8 2010

Other

Other15th International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2010
CountryItaly
CityBologna
Period9/6/109/8/10

Fingerprint

Field effect transistors
Ferroelectric materials
Capacitance
Modeling
Voltage
Feedback
Surface Potential
MOSFET
Semiconductor Devices
Insulator
Surface potential
Semiconductor devices
Threshold voltage
Leakage
Non-equilibrium
Tuning
Slope
Polarization
Doping (additives)
Fluctuations

Keywords

  • Compact modeling
  • Fe-FET
  • Random dopant fluctuation (RDF)
  • Steep subthreshold slope
  • Variation-insensitive

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Computer Science Applications
  • Modeling and Simulation

Cite this

Wang, C. C., Ye, Y., & Cao, Y. (2010). Compact modeling of Fe-FET and implications on variation-insensitive design. In International Conference on Simulation of Semiconductor Processes and Devices, SISPAD (pp. 247-250). [5604516] https://doi.org/10.1109/SISPAD.2010.5604516

Compact modeling of Fe-FET and implications on variation-insensitive design. / Wang, Chi Chao; Ye, Yun; Cao, Yu.

International Conference on Simulation of Semiconductor Processes and Devices, SISPAD. 2010. p. 247-250 5604516.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Wang, CC, Ye, Y & Cao, Y 2010, Compact modeling of Fe-FET and implications on variation-insensitive design. in International Conference on Simulation of Semiconductor Processes and Devices, SISPAD., 5604516, pp. 247-250, 15th International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2010, Bologna, Italy, 9/6/10. https://doi.org/10.1109/SISPAD.2010.5604516
Wang CC, Ye Y, Cao Y. Compact modeling of Fe-FET and implications on variation-insensitive design. In International Conference on Simulation of Semiconductor Processes and Devices, SISPAD. 2010. p. 247-250. 5604516 https://doi.org/10.1109/SISPAD.2010.5604516
Wang, Chi Chao ; Ye, Yun ; Cao, Yu. / Compact modeling of Fe-FET and implications on variation-insensitive design. International Conference on Simulation of Semiconductor Processes and Devices, SISPAD. 2010. pp. 247-250
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