Compact modeling of carbon nanotube transistor for early stage process-design exploration

Asha Balijepalli, Saurabh Sinha, Yu Cao

Research output: Chapter in Book/Report/Conference proceedingConference contribution

60 Scopus citations

Abstract

Carbon nanotube transistor (CNT) is promising to be the technology of choice for nanoscale integration. In this work, we develop the first compact model of CNT, with the objective to explore the optimal process and design space for robust low-power applications. Based on the concept of the surface potential, the new model accurately predicts the characteristics of a CNT device under various process and design conditions, such as diameter, chirality, gate dielectrics, and bias voltages. With the physical modeling of the contact, this model covers both the Schottky-barrier CNT (SB-CNT) and MOS-type CNT. The proposed model does not require any iteration and thus, significantly enhances the simulation efficiency to support large-scale design research. Using this model, we benchmark the performance of a FO4 inverter with CNT and 22nm CMOS technology. The following key insights are extracted: (1) even with the SB-CNT and realistic layout parasitics, the circuit speed can be more than 10X that of 22nm CMOS; (2) The diameter range of 1-1.5nm exhibits the maximum tolerance to contact materials and process variations; (3) a CNT circuit allows better scaling of the supply voltage (Vdd) for power reduction. For a fixed energy consumption and Vdd, the CNT speed is 4X that of 22nm CMOS. Overall, the new model enables efficient design research with CNT, revealing tremendous opportunities for both high-speed and low-power applications.

Original languageEnglish (US)
Title of host publicationISLPED'07
Subtitle of host publicationProceedings of the 2007 International Symposium on Low Power Electronics and Design
Pages2-7
Number of pages6
DOIs
StatePublished - Dec 18 2007
EventISLPED'07: 2007 International Symposium on Low Power Electronics and Design - Portland, OR, United States
Duration: Aug 27 2007Aug 29 2007

Publication series

NameProceedings of the International Symposium on Low Power Electronics and Design
ISSN (Print)1533-4678

Other

OtherISLPED'07: 2007 International Symposium on Low Power Electronics and Design
CountryUnited States
CityPortland, OR
Period8/27/078/29/07

Keywords

  • CNT
  • Modeling
  • Optimum delay
  • Process variability
  • Schottky-barrier
  • Surface potential

ASJC Scopus subject areas

  • Engineering(all)

Fingerprint Dive into the research topics of 'Compact modeling of carbon nanotube transistor for early stage process-design exploration'. Together they form a unique fingerprint.

  • Cite this

    Balijepalli, A., Sinha, S., & Cao, Y. (2007). Compact modeling of carbon nanotube transistor for early stage process-design exploration. In ISLPED'07: Proceedings of the 2007 International Symposium on Low Power Electronics and Design (pp. 2-7). (Proceedings of the International Symposium on Low Power Electronics and Design). https://doi.org/10.1145/1283780.1283783