Abstract

A compact model for the partially depleted (PD) silicon-on-insulator (SOI) metal semiconductor field effect transistor (MESFET) is presented. The absence of a gate-oxide makes the SOI MESFET extremely robust, able to withstand high voltages, and useful for extreme environment electronics. These devices have been fabricated using a standard SOI CMOS process. In contrast to SOI MOSFETs and GaAs MESFETs, the source-substrate voltage has a significant impact on the channel current. In this work a model has been developed that includes the effect of the buried oxide on the performance of the MESFET. The model has been verified for a wide temperature range of -180 to 150 °C. A behavioral model has been included to model the breakdown voltage. The core DC and RF models have been adapted from the commercially available Triquint's Own Model (TOM3) MESFET model. Building from the TOM3 model, a measurement-based approach is used to develop a four-terminal compact model using Verilog-A. The charge-based approach, using S-parameter measurements was used to develop the capacitance model. We also present a voltage reference circuit using two MESFET transistors to verify the model and explore wide temperature range circuit applications.

Original languageEnglish (US)
Pages (from-to)1264-1273
Number of pages10
JournalMicroelectronics Journal
Volume40
Issue number9
DOIs
StatePublished - Sep 2009

Fingerprint

MISFET devices
MIS (semiconductors)
Silicon
field effect transistors
silicon
MESFET devices
Temperature
temperature
Oxides
Electric potential
insulators
metals
Computer hardware description languages
oxides
Networks (circuits)
Scattering parameters
electric potential
Electric breakdown
electrical faults

Keywords

  • MESFETs
  • Silicon-on-insulator
  • SPICE model
  • TOM3 capacitance model
  • Verilog-A

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials
  • Surfaces, Coatings and Films
  • Atomic and Molecular Physics, and Optics
  • Condensed Matter Physics

Cite this

Compact modeling of a PD SOI MESFET for wide temperature designs. / Balijepalli, A.; Ervin, J.; Lepkowski, W.; Cao, Yu; Thornton, Trevor.

In: Microelectronics Journal, Vol. 40, No. 9, 09.2009, p. 1264-1273.

Research output: Contribution to journalArticle

Balijepalli, A. ; Ervin, J. ; Lepkowski, W. ; Cao, Yu ; Thornton, Trevor. / Compact modeling of a PD SOI MESFET for wide temperature designs. In: Microelectronics Journal. 2009 ; Vol. 40, No. 9. pp. 1264-1273.
@article{e02f89e6f600400f8a650a5b5d6eca36,
title = "Compact modeling of a PD SOI MESFET for wide temperature designs",
abstract = "A compact model for the partially depleted (PD) silicon-on-insulator (SOI) metal semiconductor field effect transistor (MESFET) is presented. The absence of a gate-oxide makes the SOI MESFET extremely robust, able to withstand high voltages, and useful for extreme environment electronics. These devices have been fabricated using a standard SOI CMOS process. In contrast to SOI MOSFETs and GaAs MESFETs, the source-substrate voltage has a significant impact on the channel current. In this work a model has been developed that includes the effect of the buried oxide on the performance of the MESFET. The model has been verified for a wide temperature range of -180 to 150 °C. A behavioral model has been included to model the breakdown voltage. The core DC and RF models have been adapted from the commercially available Triquint's Own Model (TOM3) MESFET model. Building from the TOM3 model, a measurement-based approach is used to develop a four-terminal compact model using Verilog-A. The charge-based approach, using S-parameter measurements was used to develop the capacitance model. We also present a voltage reference circuit using two MESFET transistors to verify the model and explore wide temperature range circuit applications.",
keywords = "MESFETs, Silicon-on-insulator, SPICE model, TOM3 capacitance model, Verilog-A",
author = "A. Balijepalli and J. Ervin and W. Lepkowski and Yu Cao and Trevor Thornton",
year = "2009",
month = "9",
doi = "10.1016/j.mejo.2008.03.014",
language = "English (US)",
volume = "40",
pages = "1264--1273",
journal = "Microelectronics",
issn = "0026-2692",
publisher = "Elsevier Limited",
number = "9",

}

TY - JOUR

T1 - Compact modeling of a PD SOI MESFET for wide temperature designs

AU - Balijepalli, A.

AU - Ervin, J.

AU - Lepkowski, W.

AU - Cao, Yu

AU - Thornton, Trevor

PY - 2009/9

Y1 - 2009/9

N2 - A compact model for the partially depleted (PD) silicon-on-insulator (SOI) metal semiconductor field effect transistor (MESFET) is presented. The absence of a gate-oxide makes the SOI MESFET extremely robust, able to withstand high voltages, and useful for extreme environment electronics. These devices have been fabricated using a standard SOI CMOS process. In contrast to SOI MOSFETs and GaAs MESFETs, the source-substrate voltage has a significant impact on the channel current. In this work a model has been developed that includes the effect of the buried oxide on the performance of the MESFET. The model has been verified for a wide temperature range of -180 to 150 °C. A behavioral model has been included to model the breakdown voltage. The core DC and RF models have been adapted from the commercially available Triquint's Own Model (TOM3) MESFET model. Building from the TOM3 model, a measurement-based approach is used to develop a four-terminal compact model using Verilog-A. The charge-based approach, using S-parameter measurements was used to develop the capacitance model. We also present a voltage reference circuit using two MESFET transistors to verify the model and explore wide temperature range circuit applications.

AB - A compact model for the partially depleted (PD) silicon-on-insulator (SOI) metal semiconductor field effect transistor (MESFET) is presented. The absence of a gate-oxide makes the SOI MESFET extremely robust, able to withstand high voltages, and useful for extreme environment electronics. These devices have been fabricated using a standard SOI CMOS process. In contrast to SOI MOSFETs and GaAs MESFETs, the source-substrate voltage has a significant impact on the channel current. In this work a model has been developed that includes the effect of the buried oxide on the performance of the MESFET. The model has been verified for a wide temperature range of -180 to 150 °C. A behavioral model has been included to model the breakdown voltage. The core DC and RF models have been adapted from the commercially available Triquint's Own Model (TOM3) MESFET model. Building from the TOM3 model, a measurement-based approach is used to develop a four-terminal compact model using Verilog-A. The charge-based approach, using S-parameter measurements was used to develop the capacitance model. We also present a voltage reference circuit using two MESFET transistors to verify the model and explore wide temperature range circuit applications.

KW - MESFETs

KW - Silicon-on-insulator

KW - SPICE model

KW - TOM3 capacitance model

KW - Verilog-A

UR - http://www.scopus.com/inward/record.url?scp=69249232311&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=69249232311&partnerID=8YFLogxK

U2 - 10.1016/j.mejo.2008.03.014

DO - 10.1016/j.mejo.2008.03.014

M3 - Article

VL - 40

SP - 1264

EP - 1273

JO - Microelectronics

JF - Microelectronics

SN - 0026-2692

IS - 9

ER -