Compact model of carbon nanotube transistor and interconnect

Saurabh Sinha, Asha Balijepalli, Yu Cao

Research output: Contribution to journalArticle

16 Scopus citations

Abstract

A noniterative physics-based compact model is developed for carbon nanotube (CNT) transistor and interconnect in order to support early stage design exploration. Based on the derivation of surface potential, the new model accurately predicts both IV and CV characteristics. It is scalable to key process and design parameters, such as the diameter, chirality, contact materials, gate dielectrics, and bias voltages. Without any iteration in model computation, the proposed model significantly enhances the simulation efficiency for large-scale design research. By benchmarking circuit performance, the optimal space of the CNT process is further localized. It is observed that for a Schottky-barrier CNT transistor with the diameter range of 1-1.5 nm, the circuit can be more than 8 × faster than that of 22-nm CMOS, with the tolerance to the variation in contact materials.

Original languageEnglish (US)
Pages (from-to)2232-2242
Number of pages11
JournalIEEE Transactions on Electron Devices
Volume56
Issue number10
DOIs
StatePublished - Sep 15 2009

Keywords

  • Carbon nanotube (CNT)
  • Interconnect
  • Modeling
  • Optimum delay
  • Process variations
  • Schottky barrier (SB)
  • Surface potential

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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