Abstract
A noniterative physics-based compact model is developed for carbon nanotube (CNT) transistor and interconnect in order to support early stage design exploration. Based on the derivation of surface potential, the new model accurately predicts both IV and CV characteristics. It is scalable to key process and design parameters, such as the diameter, chirality, contact materials, gate dielectrics, and bias voltages. Without any iteration in model computation, the proposed model significantly enhances the simulation efficiency for large-scale design research. By benchmarking circuit performance, the optimal space of the CNT process is further localized. It is observed that for a Schottky-barrier CNT transistor with the diameter range of 1-1.5 nm, the circuit can be more than 8 × faster than that of 22-nm CMOS, with the tolerance to the variation in contact materials.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 2232-2242 |
| Number of pages | 11 |
| Journal | IEEE Transactions on Electron Devices |
| Volume | 56 |
| Issue number | 10 |
| DOIs | |
| State | Published - 2009 |
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Keywords
- Carbon nanotube (CNT)
- Interconnect
- Modeling
- Optimum delay
- Process variations
- Schottky barrier (SB)
- Surface potential
ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Electronic, Optical and Magnetic Materials
Cite this
Compact model of carbon nanotube transistor and interconnect. / Sinha, Saurabh; Balijepalli, Asha; Cao, Yu.
In: IEEE Transactions on Electron Devices, Vol. 56, No. 10, 2009, p. 2232-2242.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - Compact model of carbon nanotube transistor and interconnect
AU - Sinha, Saurabh
AU - Balijepalli, Asha
AU - Cao, Yu
PY - 2009
Y1 - 2009
N2 - A noniterative physics-based compact model is developed for carbon nanotube (CNT) transistor and interconnect in order to support early stage design exploration. Based on the derivation of surface potential, the new model accurately predicts both IV and CV characteristics. It is scalable to key process and design parameters, such as the diameter, chirality, contact materials, gate dielectrics, and bias voltages. Without any iteration in model computation, the proposed model significantly enhances the simulation efficiency for large-scale design research. By benchmarking circuit performance, the optimal space of the CNT process is further localized. It is observed that for a Schottky-barrier CNT transistor with the diameter range of 1-1.5 nm, the circuit can be more than 8 × faster than that of 22-nm CMOS, with the tolerance to the variation in contact materials.
AB - A noniterative physics-based compact model is developed for carbon nanotube (CNT) transistor and interconnect in order to support early stage design exploration. Based on the derivation of surface potential, the new model accurately predicts both IV and CV characteristics. It is scalable to key process and design parameters, such as the diameter, chirality, contact materials, gate dielectrics, and bias voltages. Without any iteration in model computation, the proposed model significantly enhances the simulation efficiency for large-scale design research. By benchmarking circuit performance, the optimal space of the CNT process is further localized. It is observed that for a Schottky-barrier CNT transistor with the diameter range of 1-1.5 nm, the circuit can be more than 8 × faster than that of 22-nm CMOS, with the tolerance to the variation in contact materials.
KW - Carbon nanotube (CNT)
KW - Interconnect
KW - Modeling
KW - Optimum delay
KW - Process variations
KW - Schottky barrier (SB)
KW - Surface potential
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UR - http://www.scopus.com/inward/citedby.url?scp=70350041409&partnerID=8YFLogxK
U2 - 10.1109/TED.2009.2028625
DO - 10.1109/TED.2009.2028625
M3 - Article
AN - SCOPUS:70350041409
VL - 56
SP - 2232
EP - 2242
JO - IEEE Transactions on Electron Devices
JF - IEEE Transactions on Electron Devices
SN - 0018-9383
IS - 10
ER -