TY - JOUR
T1 - Compact model of carbon nanotube transistor and interconnect
AU - Sinha, Saurabh
AU - Balijepalli, Asha
AU - Cao, Yu
N1 - Funding Information:
The authors would like to thank the Materials, Structure, and Devices Center and also the Center of Circuits and System Solutions, two of the five research centers funded under the Focus Center Research Program, a Semiconductor Research Corporation program, for their support. The authors would also like to thank J. Deng and H.-S. P. Wong of Stanford University for their support and the discussions.
PY - 2009
Y1 - 2009
N2 - A noniterative physics-based compact model is developed for carbon nanotube (CNT) transistor and interconnect in order to support early stage design exploration. Based on the derivation of surface potential, the new model accurately predicts both IV and CV characteristics. It is scalable to key process and design parameters, such as the diameter, chirality, contact materials, gate dielectrics, and bias voltages. Without any iteration in model computation, the proposed model significantly enhances the simulation efficiency for large-scale design research. By benchmarking circuit performance, the optimal space of the CNT process is further localized. It is observed that for a Schottky-barrier CNT transistor with the diameter range of 1-1.5 nm, the circuit can be more than 8 × faster than that of 22-nm CMOS, with the tolerance to the variation in contact materials.
AB - A noniterative physics-based compact model is developed for carbon nanotube (CNT) transistor and interconnect in order to support early stage design exploration. Based on the derivation of surface potential, the new model accurately predicts both IV and CV characteristics. It is scalable to key process and design parameters, such as the diameter, chirality, contact materials, gate dielectrics, and bias voltages. Without any iteration in model computation, the proposed model significantly enhances the simulation efficiency for large-scale design research. By benchmarking circuit performance, the optimal space of the CNT process is further localized. It is observed that for a Schottky-barrier CNT transistor with the diameter range of 1-1.5 nm, the circuit can be more than 8 × faster than that of 22-nm CMOS, with the tolerance to the variation in contact materials.
KW - Carbon nanotube (CNT)
KW - Interconnect
KW - Modeling
KW - Optimum delay
KW - Process variations
KW - Schottky barrier (SB)
KW - Surface potential
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U2 - 10.1109/TED.2009.2028625
DO - 10.1109/TED.2009.2028625
M3 - Article
AN - SCOPUS:70350041409
SN - 0018-9383
VL - 56
SP - 2232
EP - 2242
JO - IEEE Transactions on Electron Devices
JF - IEEE Transactions on Electron Devices
IS - 10
ER -