Code transformations for TLB power reduction

Reiley Jeyapaul, Sandeep Marathe, Aviral Shrivastava

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

The Translation Look-aside Buffer (TLB) is a very important part in the hardware support for virtual memory management implementation of high performance embedded systems. The TLB though small is very frequently accessed, and therefore not only consumes significant energy, but also is one of the important thermal hot-spots in the processor. Recently, several circuit and microarchitectural implementations of TLBs have been proposed to reduce TLB power. One simple, yet effective TLB design for power reduction is the Use-Last TLB architecture proposed in [9]. The Use-Last TLB architecture reduces the power consumption when the last page is accessed again. While very effective for instruction TLB, this technique is not as effective for the data TLB. In this paper, we propose compiler techniques (specifically, instruction and operand reordering, array interleaving, and loop unrolling) to reduce the page switchings in data accesses. Our comprehensive page-switch reduction algorithm results in an average of 39% reduction in the data-TLB page switching, and therefore power with negligible variation in performance on benchmarks from MiBench, Multimedia, DSPStone and BDTI suites.

Original languageEnglish (US)
Title of host publicationProceedings: 22nd International Conference on VLSI Design - Held Jointly with 7th International Conference on Embedded Systems
Pages413-418
Number of pages6
DOIs
StatePublished - 2009
Event22nd International Conference on VLSI Design - Held Jointly with 7th International Conference on Embedded Systems - New Delhi, India
Duration: Jan 5 2009Jan 9 2009

Other

Other22nd International Conference on VLSI Design - Held Jointly with 7th International Conference on Embedded Systems
CountryIndia
CityNew Delhi
Period1/5/091/9/09

Fingerprint

Embedded systems
Computer hardware
Electric power utilization
Switches
Data storage equipment
Networks (circuits)
Hot Temperature

ASJC Scopus subject areas

  • Hardware and Architecture
  • Control and Systems Engineering
  • Electrical and Electronic Engineering

Cite this

Jeyapaul, R., Marathe, S., & Shrivastava, A. (2009). Code transformations for TLB power reduction. In Proceedings: 22nd International Conference on VLSI Design - Held Jointly with 7th International Conference on Embedded Systems (pp. 413-418). [4749708] https://doi.org/10.1109/VLSI.Design.2009.39

Code transformations for TLB power reduction. / Jeyapaul, Reiley; Marathe, Sandeep; Shrivastava, Aviral.

Proceedings: 22nd International Conference on VLSI Design - Held Jointly with 7th International Conference on Embedded Systems. 2009. p. 413-418 4749708.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Jeyapaul, R, Marathe, S & Shrivastava, A 2009, Code transformations for TLB power reduction. in Proceedings: 22nd International Conference on VLSI Design - Held Jointly with 7th International Conference on Embedded Systems., 4749708, pp. 413-418, 22nd International Conference on VLSI Design - Held Jointly with 7th International Conference on Embedded Systems, New Delhi, India, 1/5/09. https://doi.org/10.1109/VLSI.Design.2009.39
Jeyapaul R, Marathe S, Shrivastava A. Code transformations for TLB power reduction. In Proceedings: 22nd International Conference on VLSI Design - Held Jointly with 7th International Conference on Embedded Systems. 2009. p. 413-418. 4749708 https://doi.org/10.1109/VLSI.Design.2009.39
Jeyapaul, Reiley ; Marathe, Sandeep ; Shrivastava, Aviral. / Code transformations for TLB power reduction. Proceedings: 22nd International Conference on VLSI Design - Held Jointly with 7th International Conference on Embedded Systems. 2009. pp. 413-418
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