@inproceedings{b2c6cba5d100402e982a5033f266cae5,
title = "CMSM: An efficient and effective code management for software managed multicores",
abstract = "As we scale the number of cores in a multicore processor, scaling the memory hierarchy is a major challenge. Software Managed Multicore (SMM) architectures are one of the promising solutions. In an SMM architecture, there are no caches, and each core has only a local scratchpad memory. If all the code and data of the task mapped to a core do not fit on its local scratchpad memory, then explicit code and data management is required. In this paper, we solve the problem of efficiently managing code on an SMM architecture. We extend the state of the art by: i) correctly calculating the code management overhead, ii) even in the presence of branches in the task, and iii) developing a heuristic CMSM (Code Mapping for Software Managed multicores) that results in efficient code management execution on the local scratchpad memory. Our experimental results collected after executing applications from MiBench suite [1] on the Cell SPEs (Cell is an SMM architecture) [2], demonstrate that correct management cost calculation and branch consideration can improve performance by 12%. Our heuristic CMSM can reduce runtime in more than 80% of the cases, and by up to 20% on our set of benchmarks.",
keywords = "Code, Embedded systems, Instruction, Local memory, Multi-core processor, SPM, Scratchpad memory",
author = "Ke Bai and Jing Lu and Aviral Shrivastava and Bryce Holton",
note = "Copyright: Copyright 2014 Elsevier B.V., All rights reserved.; 11th ACM/IEEE International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2013 ; Conference date: 29-09-2013 Through 04-10-2013",
year = "2013",
doi = "10.1109/CODES-ISSS.2013.6658998",
language = "English (US)",
isbn = "9781479914173",
series = "2013 International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2013",
publisher = "IEEE Computer Society",
booktitle = "2013 International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2013",
}