CMOS process uniformity evaluation through the characterisation of parasitic transistors

D. Wilson, A. J. Walton, J. M. Robertson, R. J. Holwill

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The design and fabrication of several families of parasitic transistors available in a standard CMOS process are discussed, and their application to process control is examined. The transistors are characterized, and their extracted parameters are correlated with those obtained from CMOS devices. From these correlations it is concluded that parasitic transistors can be used to provide a more complete picture of CMOS process variation.

Original languageEnglish (US)
Title of host publicationProc 1989 Int Conf Microelectron Test Struct
Editors Anon
PublisherPubl by IEEE
Pages181-186
Number of pages6
ISBN (Print)0879427140
StatePublished - Dec 1 1989
EventProceedings of the 1989 International Conference on Microelectronic Test Structures - Edinburgh, Scotl
Duration: Mar 13 1989Mar 14 1989

Publication series

NameProc 1989 Int Conf Microelectron Test Struct

Other

OtherProceedings of the 1989 International Conference on Microelectronic Test Structures
CityEdinburgh, Scotl
Period3/13/893/14/89

ASJC Scopus subject areas

  • Engineering(all)

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