CMOS power drivers for digital transmitters: Challenges and architectures

Soroush Moallemi; Kevin Grout; Jennifer Kitchen

doi:10.1109/RWS.2019.8714222

CMOS power drivers for digital transmitters: Challenges and architectures

Soroush Moallemi, Kevin Grout, Jennifer Kitchen

Engineering, Ira A. Fulton Schools of (IAFSE)

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This paper presents two CMOS power drivers for interfacing low-voltage CMOS processing circuits to off-chip GaN switched-mode power amplifiers. The drivers employ stacked transistor configurations in a 45nm CMOS SOI technology to achieve 5V output voltage swing from 50MHz to 2GHz switching frequencies, with 20% to 80% pulse width dynamic range. The two driver architectures are compared with respect to design complexity, transient performance, silicon area, and power dissipation. Additionally, this work analyzes the implementation challenges and performance limitations when driving off-chip power devices using integrated silicon drivers.

Original language	English (US)
Title of host publication	2019 IEEE Radio and Wireless Symposium, RWS 2019
Publisher	IEEE Computer Society
ISBN (Electronic)	9781538659441
DOIs	https://doi.org/10.1109/RWS.2019.8714222
State	Published - May 14 2019
Event	2019 IEEE Radio and Wireless Symposium, RWS 2019 - Orlando, United States Duration: Jan 20 2019 → Jan 23 2019

Publication series

Name	IEEE Radio and Wireless Symposium, RWS
ISSN (Print)	2164-2958
ISSN (Electronic)	2164-2974

Conference

Conference	2019 IEEE Radio and Wireless Symposium, RWS 2019
Country	United States
City	Orlando
Period	1/20/19 → 1/23/19

Keywords

CMOS
Digital transmitter
Gan
High voltage
Power amplifier
Power driver
Switched mode

ASJC Scopus subject areas

Computer Networks and Communications
Computer Science Applications
Electrical and Electronic Engineering
Communication

Access to Document

10.1109/RWS.2019.8714222

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Cite this

Moallemi, S., Grout, K., & Kitchen, J. (2019). CMOS power drivers for digital transmitters: Challenges and architectures. In 2019 IEEE Radio and Wireless Symposium, RWS 2019 [8714222] (IEEE Radio and Wireless Symposium, RWS). IEEE Computer Society. https://doi.org/10.1109/RWS.2019.8714222

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abstract = "This paper presents two CMOS power drivers for interfacing low-voltage CMOS processing circuits to off-chip GaN switched-mode power amplifiers. The drivers employ stacked transistor configurations in a 45nm CMOS SOI technology to achieve 5V output voltage swing from 50MHz to 2GHz switching frequencies, with 20% to 80% pulse width dynamic range. The two driver architectures are compared with respect to design complexity, transient performance, silicon area, and power dissipation. Additionally, this work analyzes the implementation challenges and performance limitations when driving off-chip power devices using integrated silicon drivers.",

keywords = "CMOS, Digital transmitter, Gan, High voltage, Power amplifier, Power driver, Switched mode",

author = "Soroush Moallemi and Kevin Grout and Jennifer Kitchen",

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doi = "10.1109/RWS.2019.8714222",

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AB - This paper presents two CMOS power drivers for interfacing low-voltage CMOS processing circuits to off-chip GaN switched-mode power amplifiers. The drivers employ stacked transistor configurations in a 45nm CMOS SOI technology to achieve 5V output voltage swing from 50MHz to 2GHz switching frequencies, with 20% to 80% pulse width dynamic range. The two driver architectures are compared with respect to design complexity, transient performance, silicon area, and power dissipation. Additionally, this work analyzes the implementation challenges and performance limitations when driving off-chip power devices using integrated silicon drivers.

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