CMOS Full-Duplex Mixer-First Receiver with Adaptive Self-Interference Cancellation

A full-duplex transceiver with on-chip self-inter-ference-cancellation (SIC) is presented. The achieved SIC is 110 dB, and it is realized in three stages: RF front-end hybrid, baseband analog, and baseband digital. An integrated hybrid is used in the RF front-end which employs an adaptive tuning impedance network (TIN) to track the antenna impedance variations, achieving over 50 dB of SIC. N -path mixer-first architecture is used for the receiver to improve the linearity and to provide out of band blocker cancellation. The self-interference is further attenuated in the analog domain using the down-converted sample of the transmit signal. The analog transmit interference canceler (TIC) receives the sampled copy of the transmitted signal of the power amplifier and offers adaptive amplitude and phase adjustment for the cancellation signal, obtaining more than 20 dB on-chip cancellation in the analog domain. The last step of SIC is realized in the digital domain using a nonlinear system with memory to cancel the remnant of self-interference and distortions, resulting in 43 dB of SIC. The front-end hybrid, mixer-first receiver, and analog TIC are implemented in a CMOS 65-nm technology. Thanks to adaptive gradient decent algorithm employed in the system, the total SIC of the hybrid and TIC is more than 70 dB, which is one of the highest cancellation values achieved on the chip. The die area is 4 mm2, and the fabricated chip consumes 80 mW dc power. The average transmit power is 23 dBm, and the noise figure of the receiver in the full-duplex mode is 11 dB.