@inproceedings{f390122d3f3d4bcaa85e3b7167a6a78d,
title = "Cluster extraction for hybrid FPGA architecture in computation intensive applications",
abstract = "This paper presents experimental results on extraction of common tasks or core clusters in Control Data Flow Graphs (CDFGs) of applications, to embed them in Hybrid-FPGA environment. After removing common sub-graphs from the CDFG, remaining computations are then implemented on LUT based reconfigurable area. A new LUT based packing mechanism using live-in live-out variable analysis and scheduling information is introduced as part of routing architecture design methodology [1]. We conducted experiments on MPEG-4, Gnu Scientific, Biochemical and Molecular modeling libraries. Map report based on Spartan 2E architecture was obtained. Results show that partial reconfiguration with the use of computation cores embedded in a sea of LUTs offer the potential for massive savings in gate density and switching requirements by eliminating the need for unnecessary and redundant sub-circuit pattern configurations.",
keywords = "Common subgraph, Hybrid fpga, Packing",
author = "A. Akoglu and Dasu, {Aravind R.} and Sethuraman Panchanathan",
year = "2004",
language = "English (US)",
isbn = "1932415424",
series = "Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'04",
pages = "296",
editor = "T.P. Plaks",
booktitle = "Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'04",
note = "Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'04 ; Conference date: 21-06-2004 Through 24-06-2004",
}