This paper presents experimental results on extraction of common tasks or core clusters in Control Data Flow Graphs (CDFGs) of applications, to embed them in Hybrid-FPGA environment. After removing common sub-graphs from the CDFG, remaining computations are then implemented on LUT based reconfigurable area. A new LUT based packing mechanism using live-in live-out variable analysis and scheduling information is introduced as part of routing architecture design methodology . We conducted experiments on MPEG-4, Gnu Scientific, Biochemical and Molecular modeling libraries. Map report based on Spartan 2E architecture was obtained. Results show that partial reconfiguration with the use of computation cores embedded in a sea of LUTs offer the potential for massive savings in gate density and switching requirements by eliminating the need for unnecessary and redundant sub-circuit pattern configurations.