Circuit Simulation Based Validation of Flip-Flop Robustness to Multiple Node Charge Collection

Sandeep Shambhulingaiah, Christopher Lieb, Lawrence T. Clark

Research output: Contribution to journalArticle

4 Scopus citations

Abstract

In modern scaled process technologies a single impinging ionizing radiation particle is increasingly likely to upset multiple circuit nodes and produce logic transients that contribute to the soft error rate. Consequently, hardening flip-flops to transients at the data and control inputs, as well as to single event upsets, due to either single or multi-node upsets is increasingly important. This paper presents a circuit simulation based methodology for pre-layout hardness validation to multi-node upsets. The methodology is applied to the development of a lower power and area radiation hardened flip-flop design, as well as a number of previous hardened flip-flops. Comparison of the hardness, as measured by estimated upset cross-section, is also facilitated. The results also show the importance of specific circuit design aspects to achieving hardness. One of the comparisons to prior designs includes a comparison of the cross-section as determined by the proposed circuit simulation methodology to ion beam results.

Original languageEnglish (US)
Article number7180414
Pages (from-to)1577-1588
Number of pages12
JournalIEEE Transactions on Nuclear Science
Volume62
Issue number4
DOIs
StatePublished - Aug 1 2015

Keywords

  • Flip-flop
  • latch
  • sequential logic circuits
  • single event transient (SET)
  • single event upset (SEU)
  • soft-errors

ASJC Scopus subject areas

  • Nuclear and High Energy Physics
  • Nuclear Energy and Engineering
  • Electrical and Electronic Engineering

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