In modern scaled process technologies a single impinging ionizing radiation particle is increasingly likely to upset multiple circuit nodes and produce logic transients that contribute to the soft error rate. Consequently, hardening flip-flops to transients at the data and control inputs, as well as to single event upsets, due to either single or multi-node upsets is increasingly important. This paper presents a circuit simulation based methodology for pre-layout hardness validation to multi-node upsets. The methodology is applied to the development of a lower power and area radiation hardened flip-flop design, as well as a number of previous hardened flip-flops. Comparison of the hardness, as measured by estimated upset cross-section, is also facilitated. The results also show the importance of specific circuit design aspects to achieving hardness. One of the comparisons to prior designs includes a comparison of the cross-section as determined by the proposed circuit simulation methodology to ion beam results.
- sequential logic circuits
- single event transient (SET)
- single event upset (SEU)
ASJC Scopus subject areas
- Nuclear and High Energy Physics
- Nuclear Energy and Engineering
- Electrical and Electronic Engineering