Circuit-level modeling for concurrent testing of operational defects due to gate oxide breakdown

Jonathan R. Carter, Sule Ozev, Daniel J. Sorin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

14 Scopus citations

Abstract

As device sizes shrink and current densities increase, the probability of device failures due to gate oxide breakdown (OBD) also increases. To provide designs that are tolerant to such failures, we must investigate and understand the manifestations of this physical phenomenon at the circuit and system level. In this paper, we develop a model for operational OBD defects, and we explore how to test for faults due to OBD. For a NAND gate, we derive the necessary input conditions that excite and detect errors due to OBD defects at the gate level. We show that traditional pattern generators fail to exercise all of these defects. Finally, we show that these test patterns can be propagated and justified for a combinational circuit in a manner similar to traditional ATPG.

Original languageEnglish (US)
Title of host publicationProceedings - Design, Automation and Test in Europe, DATE '05
Pages300-305
Number of pages6
DOIs
StatePublished - Dec 1 2005
Externally publishedYes
EventDesign, Automation and Test in Europe, DATE '05 - Munich, Germany
Duration: Mar 7 2005Mar 11 2005

Publication series

NameProceedings -Design, Automation and Test in Europe, DATE '05
VolumeI
ISSN (Print)1530-1591

Other

OtherDesign, Automation and Test in Europe, DATE '05
CountryGermany
CityMunich
Period3/7/053/11/05

ASJC Scopus subject areas

  • Engineering(all)

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  • Cite this

    Carter, J. R., Ozev, S., & Sorin, D. J. (2005). Circuit-level modeling for concurrent testing of operational defects due to gate oxide breakdown. In Proceedings - Design, Automation and Test in Europe, DATE '05 (pp. 300-305). [1395575] (Proceedings -Design, Automation and Test in Europe, DATE '05; Vol. I). https://doi.org/10.1109/DATE.2005.94