@inproceedings{1f09f0f112734ccd8de97ee918cad5c7,
title = "Circuit architecture for low-power race-free programmable logic arrays",
abstract = "The design of programmable logic arrays using NAND-NOR gates for the AND and OR logic planes, respectively, instead of the conventional NOR-NOR planes is described. The circuit architecture uses a hierarchical tree of four input domino NAND gates to implement the AND plane. The OR plane is split in two for increased speed and robustness. The circuits as well as timing and power advantages are described. Simulations on a foundry 130 nm process show nearly 50% power savings at less than 10% delay cost, primarily due to lower AND plane activity factor and reduced clock loading.",
keywords = "Circuit timing, Low power, Programmable logic arrays",
author = "Giby Samson and Clark, {Lawrence T.}",
year = "2006",
month = jan,
day = "1",
doi = "10.1145/1127908.1128003",
language = "English (US)",
isbn = "1595933476",
series = "Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI",
publisher = "Association for Computing Machinery (ACM)",
pages = "416--421",
booktitle = "GLSVLSI'06 - Proceedings of the 2006 ACM Great Lakes Symposium on VLSI",
address = "United States",
note = "GLSVLSI'06 - 2006 ACM Great Lakes Symposium on VLSI ; Conference date: 30-04-2006 Through 02-05-2006",
}