Circuit architecture for low-power race-free programmable logic arrays

Giby Samson; Lawrence T. Clark

doi:10.1145/1127908.1128003

Circuit architecture for low-power race-free programmable logic arrays

Giby Samson, Lawrence T. Clark

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Scopus citations

Abstract

The design of programmable logic arrays using NAND-NOR gates for the AND and OR logic planes, respectively, instead of the conventional NOR-NOR planes is described. The circuit architecture uses a hierarchical tree of four input domino NAND gates to implement the AND plane. The OR plane is split in two for increased speed and robustness. The circuits as well as timing and power advantages are described. Simulations on a foundry 130 nm process show nearly 50% power savings at less than 10% delay cost, primarily due to lower AND plane activity factor and reduced clock loading.

Original language	English (US)
Title of host publication	GLSVLSI'06 - Proceedings of the 2006 ACM Great Lakes Symposium on VLSI
Publisher	Association for Computing Machinery (ACM)
Pages	416-421
Number of pages	6
ISBN (Print)	1595933476, 9781595933478
DOIs	https://doi.org/10.1145/1127908.1128003
State	Published - Jan 1 2006
Event	GLSVLSI'06 - 2006 ACM Great Lakes Symposium on VLSI - Philadelphia, PA, United States Duration: Apr 30 2006 → May 2 2006

Publication series

Name	Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI
Volume	2006

Conference

Conference	GLSVLSI'06 - 2006 ACM Great Lakes Symposium on VLSI
Country	United States
City	Philadelphia, PA
Period	4/30/06 → 5/2/06

Keywords

Circuit timing
Low power
Programmable logic arrays

ASJC Scopus subject areas

Engineering(all)

Access to Document

10.1145/1127908.1128003

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Circuit architecture for low-power race-free programmable logic arrays. / Samson, Giby; Clark, Lawrence T.

GLSVLSI'06 - Proceedings of the 2006 ACM Great Lakes Symposium on VLSI. Association for Computing Machinery (ACM), 2006. p. 416-421 (Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI; Vol. 2006).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Samson, G & Clark, LT 2006, Circuit architecture for low-power race-free programmable logic arrays. in GLSVLSI'06 - Proceedings of the 2006 ACM Great Lakes Symposium on VLSI. Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI, vol. 2006, Association for Computing Machinery (ACM), pp. 416-421, GLSVLSI'06 - 2006 ACM Great Lakes Symposium on VLSI, Philadelphia, PA, United States, 4/30/06. https://doi.org/10.1145/1127908.1128003

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