Circuit architecture for low-power race-free programmable logic arrays

Giby Samson, Lawrence T. Clark

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Scopus citations

Abstract

The design of programmable logic arrays using NAND-NOR gates for the AND and OR logic planes, respectively, instead of the conventional NOR-NOR planes is described. The circuit architecture uses a hierarchical tree of four input domino NAND gates to implement the AND plane. The OR plane is split in two for increased speed and robustness. The circuits as well as timing and power advantages are described. Simulations on a foundry 130 nm process show nearly 50% power savings at less than 10% delay cost, primarily due to lower AND plane activity factor and reduced clock loading.

Original languageEnglish (US)
Title of host publicationGLSVLSI'06 - Proceedings of the 2006 ACM Great Lakes Symposium on VLSI
Pages416-421
Number of pages6
StatePublished - Nov 16 2006
EventGLSVLSI'06 - 2006 ACM Great Lakes Symposium on VLSI - Philadelphia, PA, United States
Duration: Apr 30 2006May 2 2006

Publication series

NameProceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI
Volume2006

Conference

ConferenceGLSVLSI'06 - 2006 ACM Great Lakes Symposium on VLSI
CountryUnited States
CityPhiladelphia, PA
Period4/30/065/2/06

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Keywords

  • Circuit timing
  • Low power
  • Programmable logic arrays

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Samson, G., & Clark, L. T. (2006). Circuit architecture for low-power race-free programmable logic arrays. In GLSVLSI'06 - Proceedings of the 2006 ACM Great Lakes Symposium on VLSI (pp. 416-421). (Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI; Vol. 2006).