Abstract
The design of programmable logic arrays using NAND-NOR gates for the AND and OR logic planes, respectively, instead of the conventional NOR-NOR planes is described. The circuit architecture uses a hierarchical tree of four input domino NAND gates to implement the AND plane. The OR plane is split in two for increased speed and robustness. The circuits as well as timing and power advantages are described. Simulations on a foundry 130 nm process show nearly 50% power savings at less than 10% delay cost, primarily due to lower AND plane activity factor and reduced clock loading.
| Original language | English (US) |
|---|---|
| Title of host publication | GLSVLSI'06 - Proceedings of the 2006 ACM Great Lakes Symposium on VLSI |
| Pages | 416-421 |
| Number of pages | 6 |
| State | Published - Nov 16 2006 |
| Event | GLSVLSI'06 - 2006 ACM Great Lakes Symposium on VLSI - Philadelphia, PA, United States Duration: Apr 30 2006 → May 2 2006 |
Publication series
| Name | Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI |
|---|---|
| Volume | 2006 |
Conference
| Conference | GLSVLSI'06 - 2006 ACM Great Lakes Symposium on VLSI |
|---|---|
| Country | United States |
| City | Philadelphia, PA |
| Period | 4/30/06 → 5/2/06 |
Fingerprint
Keywords
- Circuit timing
- Low power
- Programmable logic arrays
ASJC Scopus subject areas
- Engineering(all)
Cite this
Samson, G., & Clark, L. T. (2006). Circuit architecture for low-power race-free programmable logic arrays. In GLSVLSI'06 - Proceedings of the 2006 ACM Great Lakes Symposium on VLSI (pp. 416-421). (Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI; Vol. 2006).