Circuit architecture for low-power race-free programmable logic arrays

Giby Samson; Lawrence T. Clark

doi:10.1145/1127908.1128003

Circuit architecture for low-power race-free programmable logic arrays

Giby Samson, Lawrence T. Clark

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Scopus citations

Abstract

The design of programmable logic arrays using NAND-NOR gates for the AND and OR logic planes, respectively, instead of the conventional NOR-NOR planes is described. The circuit architecture uses a hierarchical tree of four input domino NAND gates to implement the AND plane. The OR plane is split in two for increased speed and robustness. The circuits as well as timing and power advantages are described. Simulations on a foundry 130 nm process show nearly 50% power savings at less than 10% delay cost, primarily due to lower AND plane activity factor and reduced clock loading.

Original language	English (US)
Title of host publication	GLSVLSI'06 - Proceedings of the 2006 ACM Great Lakes Symposium on VLSI
Publisher	Association for Computing Machinery (ACM)
Pages	416-421
Number of pages	6
ISBN (Print)	1595933476, 9781595933478
DOIs	https://doi.org/10.1145/1127908.1128003
State	Published - Jan 1 2006
Event	GLSVLSI'06 - 2006 ACM Great Lakes Symposium on VLSI - Philadelphia, PA, United States Duration: Apr 30 2006 → May 2 2006

Publication series

Name	Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI
Volume	2006

Conference

Conference	GLSVLSI'06 - 2006 ACM Great Lakes Symposium on VLSI
Country/Territory	United States
City	Philadelphia, PA
Period	4/30/06 → 5/2/06

Keywords

Circuit timing
Low power
Programmable logic arrays

ASJC Scopus subject areas

Engineering(all)

Access to Document

10.1145/1127908.1128003

Cite this

Circuit architecture for low-power race-free programmable logic arrays. / Samson, Giby; Clark, Lawrence T.

GLSVLSI'06 - Proceedings of the 2006 ACM Great Lakes Symposium on VLSI. Association for Computing Machinery (ACM), 2006. p. 416-421 (Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI; Vol. 2006).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Samson, G & Clark, LT 2006, Circuit architecture for low-power race-free programmable logic arrays. in GLSVLSI'06 - Proceedings of the 2006 ACM Great Lakes Symposium on VLSI. Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI, vol. 2006, Association for Computing Machinery (ACM), pp. 416-421, GLSVLSI'06 - 2006 ACM Great Lakes Symposium on VLSI, Philadelphia, PA, United States, 4/30/06. https://doi.org/10.1145/1127908.1128003

@inproceedings{1f09f0f112734ccd8de97ee918cad5c7,

title = "Circuit architecture for low-power race-free programmable logic arrays",

abstract = "The design of programmable logic arrays using NAND-NOR gates for the AND and OR logic planes, respectively, instead of the conventional NOR-NOR planes is described. The circuit architecture uses a hierarchical tree of four input domino NAND gates to implement the AND plane. The OR plane is split in two for increased speed and robustness. The circuits as well as timing and power advantages are described. Simulations on a foundry 130 nm process show nearly 50% power savings at less than 10% delay cost, primarily due to lower AND plane activity factor and reduced clock loading.",

keywords = "Circuit timing, Low power, Programmable logic arrays",

author = "Giby Samson and Clark, {Lawrence T.}",

year = "2006",

month = jan,

day = "1",

doi = "10.1145/1127908.1128003",

language = "English (US)",

isbn = "1595933476",

series = "Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI",

publisher = "Association for Computing Machinery (ACM)",

pages = "416--421",

booktitle = "GLSVLSI'06 - Proceedings of the 2006 ACM Great Lakes Symposium on VLSI",

address = "United States",

note = "GLSVLSI'06 - 2006 ACM Great Lakes Symposium on VLSI ; Conference date: 30-04-2006 Through 02-05-2006",

}

TY - GEN

T1 - Circuit architecture for low-power race-free programmable logic arrays

AU - Samson, Giby

AU - Clark, Lawrence T.

PY - 2006/1/1

Y1 - 2006/1/1

N2 - The design of programmable logic arrays using NAND-NOR gates for the AND and OR logic planes, respectively, instead of the conventional NOR-NOR planes is described. The circuit architecture uses a hierarchical tree of four input domino NAND gates to implement the AND plane. The OR plane is split in two for increased speed and robustness. The circuits as well as timing and power advantages are described. Simulations on a foundry 130 nm process show nearly 50% power savings at less than 10% delay cost, primarily due to lower AND plane activity factor and reduced clock loading.

AB - The design of programmable logic arrays using NAND-NOR gates for the AND and OR logic planes, respectively, instead of the conventional NOR-NOR planes is described. The circuit architecture uses a hierarchical tree of four input domino NAND gates to implement the AND plane. The OR plane is split in two for increased speed and robustness. The circuits as well as timing and power advantages are described. Simulations on a foundry 130 nm process show nearly 50% power savings at less than 10% delay cost, primarily due to lower AND plane activity factor and reduced clock loading.

KW - Circuit timing

KW - Low power

KW - Programmable logic arrays

UR - http://www.scopus.com/inward/record.url?scp=33750902009&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=33750902009&partnerID=8YFLogxK

U2 - 10.1145/1127908.1128003

DO - 10.1145/1127908.1128003

M3 - Conference contribution

AN - SCOPUS:33750902009

SN - 1595933476

SN - 9781595933478

T3 - Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

SP - 416

EP - 421

BT - GLSVLSI'06 - Proceedings of the 2006 ACM Great Lakes Symposium on VLSI

PB - Association for Computing Machinery (ACM)

T2 - GLSVLSI'06 - 2006 ACM Great Lakes Symposium on VLSI

Y2 - 30 April 2006 through 2 May 2006

ER -

Circuit architecture for low-power race-free programmable logic arrays

Abstract

Publication series

Conference

Keywords

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this