Chip hierarchical design system (CHDS): a foundation for timing-driven physical design into the 21st century

R. G. Bushroe, S. DasGupta, A. Dengi, P. Fisher, S. Grout, G. Ledenbach, N. S. Nagaraj, R. Steele

Research output: Contribution to conferencePaper

7 Scopus citations

Abstract

This paper presents the description of the architecture of the Chip Hierarchical Design System (CHDS) and details on the required Timing Driven Physical Design capabilities that have been defined to satisfy the physical design needs for 0.25μ technologies and beyond. These requirements are intended to solve the challenges including the Design Productivity Crisis identified by semiconductor industry, the shift in the design paradigm where the timing of a physical design will be dominated by interconnect effects, and the need for an integrated physical design system which still supports 'plug-and-play' through the use of EDA standard languages, models, and interfaces.

Original languageEnglish (US)
Pages212-217
Number of pages6
StatePublished - Jan 1 1997
EventProceedings of the 1997 1st International Symposium on Physical Design, ISPD - Napa Valley, CA, USA
Duration: Apr 14 1997Apr 16 1997

Other

OtherProceedings of the 1997 1st International Symposium on Physical Design, ISPD
CityNapa Valley, CA, USA
Period4/14/974/16/97

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ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Bushroe, R. G., DasGupta, S., Dengi, A., Fisher, P., Grout, S., Ledenbach, G., Nagaraj, N. S., & Steele, R. (1997). Chip hierarchical design system (CHDS): a foundation for timing-driven physical design into the 21st century. 212-217. Paper presented at Proceedings of the 1997 1st International Symposium on Physical Design, ISPD, Napa Valley, CA, USA, .