Charge trapping in MOSFETS: BTI and RTN modeling for circuits

Gilson Wirth, Yu Cao, Jyothi B. Velamala, Ketul B. Sutaria, Takashi Sato

Research output: Chapter in Book/Report/Conference proceedingChapter

3 Scopus citations

Abstract

This chapter presents experimental investigation and statistical modeling of charge trapping in the context of random telegraph noise (RTN) and bias temperature instability (BTI). The goal is to develop circuit (electrical) level models to support circuit designers. The developed modeling approach is based on discrete device physics quantities, which are shown to cause statistical variability in the electrical behavior of MOSFETs. Besides evaluating the average behavior, the modeling approach here proposed allows the derivation of statistically relevant parameters. It allows the derivation of an analytical formulation for the both noise (RTN) and aging (BTI) behavior. Monte Carlo simulations are also discussed and presented. Good agreement between experimental data, Monte Carlo simulations, and model is found.

Original languageEnglish (US)
Title of host publicationBias Temperature Instability for Devices and Circuits
PublisherSpringer New York
Pages751-782
Number of pages32
ISBN (Print)9781461479093, 1461479088, 9781461479086
DOIs
Publication statusPublished - Jul 1 2014

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ASJC Scopus subject areas

  • Engineering(all)

Cite this

Wirth, G., Cao, Y., Velamala, J. B., Sutaria, K. B., & Sato, T. (2014). Charge trapping in MOSFETS: BTI and RTN modeling for circuits. In Bias Temperature Instability for Devices and Circuits (pp. 751-782). Springer New York. https://doi.org/10.1007/978-1-4614-7909-3_29