Charge trapping in MOSFETS

BTI and RTN modeling for circuits

Gilson Wirth, Yu Cao, Jyothi B. Velamala, Ketul B. Sutaria, Takashi Sato

Research output: Chapter in Book/Report/Conference proceedingChapter

3 Citations (Scopus)

Abstract

This chapter presents experimental investigation and statistical modeling of charge trapping in the context of random telegraph noise (RTN) and bias temperature instability (BTI). The goal is to develop circuit (electrical) level models to support circuit designers. The developed modeling approach is based on discrete device physics quantities, which are shown to cause statistical variability in the electrical behavior of MOSFETs. Besides evaluating the average behavior, the modeling approach here proposed allows the derivation of statistically relevant parameters. It allows the derivation of an analytical formulation for the both noise (RTN) and aging (BTI) behavior. Monte Carlo simulations are also discussed and presented. Good agreement between experimental data, Monte Carlo simulations, and model is found.

Original languageEnglish (US)
Title of host publicationBias Temperature Instability for Devices and Circuits
PublisherSpringer New York
Pages751-782
Number of pages32
ISBN (Print)9781461479093, 1461479088, 9781461479086
DOIs
StatePublished - Jul 1 2014

Fingerprint

Telegraph
Charge trapping
Networks (circuits)
Physics
Aging of materials
Temperature
Monte Carlo simulation

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Wirth, G., Cao, Y., Velamala, J. B., Sutaria, K. B., & Sato, T. (2014). Charge trapping in MOSFETS: BTI and RTN modeling for circuits. In Bias Temperature Instability for Devices and Circuits (pp. 751-782). Springer New York. https://doi.org/10.1007/978-1-4614-7909-3_29

Charge trapping in MOSFETS : BTI and RTN modeling for circuits. / Wirth, Gilson; Cao, Yu; Velamala, Jyothi B.; Sutaria, Ketul B.; Sato, Takashi.

Bias Temperature Instability for Devices and Circuits. Springer New York, 2014. p. 751-782.

Research output: Chapter in Book/Report/Conference proceedingChapter

Wirth, G, Cao, Y, Velamala, JB, Sutaria, KB & Sato, T 2014, Charge trapping in MOSFETS: BTI and RTN modeling for circuits. in Bias Temperature Instability for Devices and Circuits. Springer New York, pp. 751-782. https://doi.org/10.1007/978-1-4614-7909-3_29
Wirth G, Cao Y, Velamala JB, Sutaria KB, Sato T. Charge trapping in MOSFETS: BTI and RTN modeling for circuits. In Bias Temperature Instability for Devices and Circuits. Springer New York. 2014. p. 751-782 https://doi.org/10.1007/978-1-4614-7909-3_29
Wirth, Gilson ; Cao, Yu ; Velamala, Jyothi B. ; Sutaria, Ketul B. ; Sato, Takashi. / Charge trapping in MOSFETS : BTI and RTN modeling for circuits. Bias Temperature Instability for Devices and Circuits. Springer New York, 2014. pp. 751-782
@inbook{e5226a6e3d0c43fa9db4cc822ed48a2d,
title = "Charge trapping in MOSFETS: BTI and RTN modeling for circuits",
abstract = "This chapter presents experimental investigation and statistical modeling of charge trapping in the context of random telegraph noise (RTN) and bias temperature instability (BTI). The goal is to develop circuit (electrical) level models to support circuit designers. The developed modeling approach is based on discrete device physics quantities, which are shown to cause statistical variability in the electrical behavior of MOSFETs. Besides evaluating the average behavior, the modeling approach here proposed allows the derivation of statistically relevant parameters. It allows the derivation of an analytical formulation for the both noise (RTN) and aging (BTI) behavior. Monte Carlo simulations are also discussed and presented. Good agreement between experimental data, Monte Carlo simulations, and model is found.",
author = "Gilson Wirth and Yu Cao and Velamala, {Jyothi B.} and Sutaria, {Ketul B.} and Takashi Sato",
year = "2014",
month = "7",
day = "1",
doi = "10.1007/978-1-4614-7909-3_29",
language = "English (US)",
isbn = "9781461479093",
pages = "751--782",
booktitle = "Bias Temperature Instability for Devices and Circuits",
publisher = "Springer New York",

}

TY - CHAP

T1 - Charge trapping in MOSFETS

T2 - BTI and RTN modeling for circuits

AU - Wirth, Gilson

AU - Cao, Yu

AU - Velamala, Jyothi B.

AU - Sutaria, Ketul B.

AU - Sato, Takashi

PY - 2014/7/1

Y1 - 2014/7/1

N2 - This chapter presents experimental investigation and statistical modeling of charge trapping in the context of random telegraph noise (RTN) and bias temperature instability (BTI). The goal is to develop circuit (electrical) level models to support circuit designers. The developed modeling approach is based on discrete device physics quantities, which are shown to cause statistical variability in the electrical behavior of MOSFETs. Besides evaluating the average behavior, the modeling approach here proposed allows the derivation of statistically relevant parameters. It allows the derivation of an analytical formulation for the both noise (RTN) and aging (BTI) behavior. Monte Carlo simulations are also discussed and presented. Good agreement between experimental data, Monte Carlo simulations, and model is found.

AB - This chapter presents experimental investigation and statistical modeling of charge trapping in the context of random telegraph noise (RTN) and bias temperature instability (BTI). The goal is to develop circuit (electrical) level models to support circuit designers. The developed modeling approach is based on discrete device physics quantities, which are shown to cause statistical variability in the electrical behavior of MOSFETs. Besides evaluating the average behavior, the modeling approach here proposed allows the derivation of statistically relevant parameters. It allows the derivation of an analytical formulation for the both noise (RTN) and aging (BTI) behavior. Monte Carlo simulations are also discussed and presented. Good agreement between experimental data, Monte Carlo simulations, and model is found.

UR - http://www.scopus.com/inward/record.url?scp=84929618987&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84929618987&partnerID=8YFLogxK

U2 - 10.1007/978-1-4614-7909-3_29

DO - 10.1007/978-1-4614-7909-3_29

M3 - Chapter

SN - 9781461479093

SN - 1461479088

SN - 9781461479086

SP - 751

EP - 782

BT - Bias Temperature Instability for Devices and Circuits

PB - Springer New York

ER -