Characterization of Parasitic Transistors to Evaluate CMOS Process Uniformity

David Wilson, Anthony J. Walton, John M. Robertson, Robert J. Holwill

Research output: Contribution to journalArticle

Abstract

The design and fabrication of several families of parasitic transistors available in a standard CMOS process are discussed and their application to process control examined. These transistors are characterized and their extracted parameters correlated with those obtained from CMOS devices. From these correlations it is concluded that parasitic transistors are very sensitive to changes in the process that influence the performance of MOS transistors. As a result parasitic transistors can be used in conjunction with standard MOS devices and test structures to provide a more complete picture of CMOS process variation.

Original languageEnglish (US)
Pages (from-to)241-249
Number of pages9
JournalIEEE Transactions on Semiconductor Manufacturing
Volume4
Issue number3
DOIs
StatePublished - Aug 1991

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Industrial and Manufacturing Engineering
  • Electrical and Electronic Engineering

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