Characterization and debug of reverse-body bias low-power modes

The relevant physics, the approaches to RBB debug and characterization that the authors expect to be applicable to processes beyond the 130 nm technology node, and the insights gained from our experience in debugging multiple RBB-equipped devices on different processes has been reported. Gate-induced drain leakage (GIDL) at the gate-drain edge is important at low current levels and high applied voltages. Transistor scaling requires increasingly steep halo doping profiles to control DIBL. These increase band-to-band (Zener) tunneling currents at the drain-to-channel edge, particularly as the drain-to-bulk bias is increased. Scan is very useful in this characterization but is limited by the difficulty of achieving complete coverage. Modern design projects employ a large array of tools to prevent incorporation of bugs into the design. Application of these techniques enables identification and correction of design errors on circuits using present-day process technology.