Abstract

Future VLSI scaling realization of gate lengths is expected to 70 nm and below. While we do not know all the underlying physics, we are beginning to understand some limiting factors, which include quantum transport, in these structures. The discrete nature of impurities, the fact that devices have critical lengths comparable to their coherence lengths, and size quantization will all be important in these structures. These phenomena will lead to pockets of charge, which will appear as coupled quantum dots in the device transport. We review some of the physics of these dots.

Original languageEnglish (US)
Pages (from-to)1841-1845
Number of pages5
JournalJapanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers
Volume36
Issue number3 SUPPL. B
StatePublished - Mar 1 1997

    Fingerprint

Keywords

  • Device modeling
  • Device physics
  • Inhomgeneities
  • Quantum dots
  • Quantum transport
  • Random impurities

ASJC Scopus subject areas

  • Engineering(all)
  • Physics and Astronomy(all)

Cite this

Ferry, D. K., Akis, R., Udipi, S., Vasileska, D., Pivin, D. P., Connolly, K. M., Bird, J. P., Ishibashi, K., Aoyagi, Y., Sugano, T., & Ochiai, Y. (1997). Carrier transport in nanodevices. Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers, 36(3 SUPPL. B), 1841-1845.