Can silicon FinFETs satisfy ITRS projections for high performance 10 nm devices?

H. Khan, D. Mamaluy, Dragica Vasileska

Research output: Contribution to journalArticle

Abstract

We utilize a fully self-consistent quantum mechanical simulator based on CBR method to optimize 10 nm FinFET devices to meet ITRS projections for High Performance (HP) logic technology devices. Fin width, gate oxide thickness, and doping profiles are chosen to reflect realistic values. We find that the device on-current approaching the value projected by ITRS for HP devices can be obtained using unstrained conventional (Si) channel. Our simulation results also show that quantum nature of transport in ultra small devices significantly enhances the intrinsic switching speed of the device. In addition, small signal analysis has been performed. Sensitivity of device performance to the process variation at room temperature has also been investigated.

Original languageEnglish (US)
Pages (from-to)284-287
Number of pages4
JournalJournal of Computational Electronics
Volume7
Issue number3
DOIs
StatePublished - 2008

Fingerprint

Signal analysis
Silicon
Oxides
High Performance
Simulators
projection
Doping (additives)
Projection
silicon
Temperature
Process Variation
Signal Analysis
signal analysis
fins
FinFET
simulators
logic
Simulator
Optimise
Logic

Keywords

  • CBR
  • Device optimization
  • FinFETs
  • Intrinsic switching speed
  • Process variation

ASJC Scopus subject areas

  • Computational Theory and Mathematics
  • Electrical and Electronic Engineering

Cite this

Can silicon FinFETs satisfy ITRS projections for high performance 10 nm devices? / Khan, H.; Mamaluy, D.; Vasileska, Dragica.

In: Journal of Computational Electronics, Vol. 7, No. 3, 2008, p. 284-287.

Research output: Contribution to journalArticle

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