Cache vulnerability equations for protecting data in embedded processor caches from soft errors

Aviral Shrivastava, Jongeun Lee, Reiley Jeyapaul

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Scopus citations

Abstract

Continuous technology scaling has brought us to a point, where transistors have become extremely susceptible to cosmic radiation strikes, or soft errors. Inside the processor, caches are most vulnerable to soft errors, and techniques at various levels of design abstraction, e.g., fabrication, gate design, circuit design, and microarchitecture-level, have been developed to protect data in caches. However, no work has been done to investigate the effect of code transformations on the vulnerability of data in caches. Data is vulnerable to soft errors in the cache only if it will be read by the processor, and not if it will be overwritten. Since code transformations can change the read-write pattern of program variables, they significantly effect the soft error vulnerability of program variables in the cache. We observe that often opportunity exists to significantly reduce the soft error vulnerability of cache data by trading-off a little performance. However, even if one wanted to exploit this trade-off, it is difficult, since there are no efficient techniques to estimate vulnerability of data in caches. To this end, this paper develops efficient static analysis method to estimate program vulnerability in caches, which enables the compiler to exploit the performance-vulnerability trade-offs in applications. Finally, as compared to simulation based estimation, static analysis techniques provide the insights into vulnerability calculations that provide some simple schemes to reduce program vulnerability.

Original languageEnglish (US)
Title of host publicationLCTES'10 - Proceedings of the ACM SIGPLAN/SIGBED 2010 Conference on Languages, Compilers, and Tools for Embedded Systems
Pages143-152
Number of pages10
DOIs
StatePublished - Jul 16 2010
EventACM SIGPLAN/SIGBED Conference on Languages, Compilers and Tools for Embedded Systems, LCTES 2010 - Stockholm, Sweden
Duration: Apr 13 2010Apr 15 2010

Publication series

NameProceedings of the ACM SIGPLAN Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES)

Conference

ConferenceACM SIGPLAN/SIGBED Conference on Languages, Compilers and Tools for Embedded Systems, LCTES 2010
CountrySweden
CityStockholm
Period4/13/104/15/10

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Keywords

  • cache vulnerability
  • code transformation
  • compiler technique
  • embedded processors
  • soft errors
  • static analysis

ASJC Scopus subject areas

  • Software

Cite this

Shrivastava, A., Lee, J., & Jeyapaul, R. (2010). Cache vulnerability equations for protecting data in embedded processor caches from soft errors. In LCTES'10 - Proceedings of the ACM SIGPLAN/SIGBED 2010 Conference on Languages, Compilers, and Tools for Embedded Systems (pp. 143-152). (Proceedings of the ACM SIGPLAN Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES)). https://doi.org/10.1145/1755888.1755910