Cache design and exploration for low power embedded systems

Research output: Chapter in Book/Report/Conference proceedingConference contribution

12 Scopus citations

Abstract

This paper summarizes our work on memory design and exploration for low power data-dominated embedded systems. The memory sub-system consists of an instruction cache and a data cache on-chip, and a large memory off-chip. Our procedure consists of (a) reducing the power consumption due to memory traffic by applying memory-optimizing loop transformations, and (b) using a memory exploration procedure to choose a cache configuration (cache size and line size) that satisfies the system requirements of area, number of cycles and energy consumption. The memory exploration procedure is very efficient since it exploits the trends in the cycles and energy characteristics to reduce the search space significantly.

Original languageEnglish (US)
Title of host publicationIEEE International Performance, Computing and Communications Conference, Proceedings
Pages135-139
Number of pages5
StatePublished - 2001
Event20th IEEE International Performance, Computing, and Communications Conference - Phoenix, AZ, United States
Duration: Apr 4 2001Apr 6 2001

Other

Other20th IEEE International Performance, Computing, and Communications Conference
CountryUnited States
CityPhoenix, AZ
Period4/4/014/6/01

ASJC Scopus subject areas

  • Media Technology

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    Chakrabarti, C. (2001). Cache design and exploration for low power embedded systems. In IEEE International Performance, Computing and Communications Conference, Proceedings (pp. 135-139)