C3SRAM: In-memory-computing sram macro based on capacitive-coupling computing

Zhewei Jiang; Shihui Yin; Jae Sun Seo; Mingoo Seok

doi:10.1109/LSSC.2019.2934831

C3SRAM: In-memory-computing sram macro based on capacitive-coupling computing

Zhewei Jiang, Shihui Yin, Jae Sun Seo, Mingoo Seok

Research output: Contribution to journal › Article › peer-review

38 Scopus citations

Abstract

This letter presents C3SRAM, an in-memory-computing SRAM macro, which utilizes analog-mixed-signal capacitive-coupling computing to perform XNOR-and-accumulate operations for binary deep neural networks. The 256 × 64 C3SRAM macro asserts all 256 rows simultaneously and equips one ADC per column, realizing fully parallel vector-matrix multiplication in one cycle. C3SRAM demonstrates 672 TOPS/W and 1638 GOPS, and achieves 98.3% accuracy for MNIST and 85.5% for CIFAR-10 dataset. It achieves 3975 × smaller energy-delay product than conventional digital processors.

Original language	English (US)
Article number	8877969
Pages (from-to)	131-134
Number of pages	4
Journal	IEEE Solid-State Circuits Letters
Volume	2
Issue number	9
DOIs	https://doi.org/10.1109/LSSC.2019.2934831
State	Published - Sep 2019

Keywords

Capacitive coupling
In-memory-computing (IMC)
Machine learning accelerator
Mixed-signal processingc
Neural network

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/LSSC.2019.2934831

Cite this

@article{3421d55add6f481582aa42e72b6fcc36,

title = "C3SRAM: In-memory-computing sram macro based on capacitive-coupling computing",

abstract = "This letter presents C3SRAM, an in-memory-computing SRAM macro, which utilizes analog-mixed-signal capacitive-coupling computing to perform XNOR-and-accumulate operations for binary deep neural networks. The 256 × 64 C3SRAM macro asserts all 256 rows simultaneously and equips one ADC per column, realizing fully parallel vector-matrix multiplication in one cycle. C3SRAM demonstrates 672 TOPS/W and 1638 GOPS, and achieves 98.3% accuracy for MNIST and 85.5% for CIFAR-10 dataset. It achieves 3975 × smaller energy-delay product than conventional digital processors.",

keywords = "Capacitive coupling, In-memory-computing (IMC), Machine learning accelerator, Mixed-signal processingc, Neural network",

author = "Zhewei Jiang and Shihui Yin and Seo, {Jae Sun} and Mingoo Seok",

note = "Publisher Copyright: {\textcopyright} 2018 IEEE.",

year = "2019",

month = sep,

doi = "10.1109/LSSC.2019.2934831",

language = "English (US)",

volume = "2",

pages = "131--134",

journal = "IEEE Solid-State Circuits Letters",

issn = "2573-9603",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "9",

}

TY - JOUR

T1 - C3SRAM

T2 - In-memory-computing sram macro based on capacitive-coupling computing

AU - Jiang, Zhewei

AU - Yin, Shihui

AU - Seo, Jae Sun

AU - Seok, Mingoo

PY - 2019/9

Y1 - 2019/9

N2 - This letter presents C3SRAM, an in-memory-computing SRAM macro, which utilizes analog-mixed-signal capacitive-coupling computing to perform XNOR-and-accumulate operations for binary deep neural networks. The 256 × 64 C3SRAM macro asserts all 256 rows simultaneously and equips one ADC per column, realizing fully parallel vector-matrix multiplication in one cycle. C3SRAM demonstrates 672 TOPS/W and 1638 GOPS, and achieves 98.3% accuracy for MNIST and 85.5% for CIFAR-10 dataset. It achieves 3975 × smaller energy-delay product than conventional digital processors.

AB - This letter presents C3SRAM, an in-memory-computing SRAM macro, which utilizes analog-mixed-signal capacitive-coupling computing to perform XNOR-and-accumulate operations for binary deep neural networks. The 256 × 64 C3SRAM macro asserts all 256 rows simultaneously and equips one ADC per column, realizing fully parallel vector-matrix multiplication in one cycle. C3SRAM demonstrates 672 TOPS/W and 1638 GOPS, and achieves 98.3% accuracy for MNIST and 85.5% for CIFAR-10 dataset. It achieves 3975 × smaller energy-delay product than conventional digital processors.

KW - Capacitive coupling

KW - In-memory-computing (IMC)

KW - Machine learning accelerator

KW - Mixed-signal processingc

KW - Neural network

UR - http://www.scopus.com/inward/record.url?scp=85092232509&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85092232509&partnerID=8YFLogxK

U2 - 10.1109/LSSC.2019.2934831

DO - 10.1109/LSSC.2019.2934831

M3 - Article

AN - SCOPUS:85092232509

SN - 2573-9603

VL - 2

SP - 131

EP - 134

JO - IEEE Solid-State Circuits Letters

JF - IEEE Solid-State Circuits Letters

IS - 9

M1 - 8877969

ER -

C3SRAM: In-memory-computing sram macro based on capacitive-coupling computing

Abstract

Keywords

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