C3SRAM: In-memory-computing sram macro based on capacitive-coupling computing

Zhewei Jiang, Shihui Yin, Jae Sun Seo, Mingoo Seok

Research output: Contribution to journalArticlepeer-review

4 Scopus citations

Abstract

This letter presents C3SRAM, an in-memory-computing SRAM macro, which utilizes analog-mixed-signal capacitive-coupling computing to perform XNOR-and-accumulate operations for binary deep neural networks. The 256 × 64 C3SRAM macro asserts all 256 rows simultaneously and equips one ADC per column, realizing fully parallel vector-matrix multiplication in one cycle. C3SRAM demonstrates 672 TOPS/W and 1638 GOPS, and achieves 98.3% accuracy for MNIST and 85.5% for CIFAR-10 dataset. It achieves 3975 × smaller energy-delay product than conventional digital processors.

Original languageEnglish (US)
Article number8877969
Pages (from-to)131-134
Number of pages4
JournalIEEE Solid-State Circuits Letters
Volume2
Issue number9
DOIs
StatePublished - Sep 2019

Keywords

  • Capacitive coupling
  • In-memory-computing (IMC)
  • Machine learning accelerator
  • Mixed-signal processingc
  • Neural network

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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