TY - GEN
T1 - C3SRAM
T2 - 45th IEEE European Solid State Circuits Conference, ESSCIRC 2019
AU - Jiang, Zhewei
AU - Yin, Shihui
AU - Seo, Jae Sun
AU - Seok, Mingoo
N1 - Funding Information:
Manuscript received May 30, 2019; revised August 1, 2019; accepted August 7, 2019. Date of publication October 15, 2019; date of current version October 15, 2019. This article was approved by Associate Editor Tobias Gemmeke. This work was supported by Wei Family Private Foundation. (Corresponding author: Zhewei Jiang.) Z. Jiang and M. Seok are with the Electrical Engineering Department, Columbia University, New York, NY 10027 USA (e-mail: zj2139@columbia.edu).
Publisher Copyright:
© 2019 IEEE.
PY - 2019/9
Y1 - 2019/9
N2 - This letter presents C3SRAM,an in-memory-computing SRAM macro,which utilizes analog-mixed-signal capacitive-coupling computing to perform XNOR-and-accumulate operations for binary deep neural networks. The 256 × 64 C3SRAM macro asserts all 256 rows simultaneously and equips one ADC per column,realizing fully parallel vector-matrix multiplication in one cycle. C3SRAM demonstrates 672 TOPS/W and 1638 GOPS,and achieves 98.3% accuracy for MNIST and 85.5% for CIFAR-10 dataset. It achieves 3975× smaller energy-delay product than conventional digital processors.
AB - This letter presents C3SRAM,an in-memory-computing SRAM macro,which utilizes analog-mixed-signal capacitive-coupling computing to perform XNOR-and-accumulate operations for binary deep neural networks. The 256 × 64 C3SRAM macro asserts all 256 rows simultaneously and equips one ADC per column,realizing fully parallel vector-matrix multiplication in one cycle. C3SRAM demonstrates 672 TOPS/W and 1638 GOPS,and achieves 98.3% accuracy for MNIST and 85.5% for CIFAR-10 dataset. It achieves 3975× smaller energy-delay product than conventional digital processors.
KW - Capacitive coupling
KW - in-memory-computing (IMC)
KW - machine learning accelerator
KW - mixed-signal processing
KW - neural network
UR - http://www.scopus.com/inward/record.url?scp=85075946978&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85075946978&partnerID=8YFLogxK
U2 - 10.1109/ESSCIRC.2019.8902752
DO - 10.1109/ESSCIRC.2019.8902752
M3 - Conference contribution
AN - SCOPUS:85075946978
T3 - ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference
SP - 131
EP - 134
BT - ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 23 September 2019 through 26 September 2019
ER -