C3SRAM: An In-Memory-Computing SRAM Macro Based on Robust Capacitive Coupling Computing Mechanism

Zhewei Jiang, Shihui Yin, Jae Sun Seo, Mingoo Seok

Research output: Contribution to journalArticlepeer-review

9 Scopus citations

Abstract

This article presents C3SRAM, an in-memory-computing SRAM macro. The macro is an SRAM module with the circuits embedded in bitcells and peripherals to perform hardware acceleration for neural networks with binarized weights and activations. The macro utilizes analog-mixed-signal (AMS) capacitive-coupling computing to evaluate the main computations of binary neural networks, binary-multiply-and-accumulate operations. Without the need to access the stored weights by individual row, the macro asserts all its rows simultaneously and forms an analog voltage at the read bitline node through capacitive voltage division. With one analog-to-digital converter (ADC) per column, the macro realizes fully parallel vector-matrix multiplication in a single cycle. The network type that the macro supports and the computing mechanism it utilizes are determined by the robustness and error tolerance necessary in AMS computing. The C3SRAM macro is prototyped in a 65-nm CMOS. It demonstrates an energy efficiency of 672 TOPS/W and a speed of 1638 GOPS (20.2 TOPS/mm2), achieving 3975 × better energy-delay product than the conventional digital baseline performing the same operation. The macro achieves 98.3% accuracy for MNIST and 85.5% for CIFAR-10, which is among the best in-memory computing works in terms of energy efficiency and inference accuracy tradeoff.

Original languageEnglish (US)
Article number9094713
Pages (from-to)1888-1897
Number of pages10
JournalIEEE Journal of Solid-State Circuits
Volume55
Issue number7
DOIs
StatePublished - Jul 2020

Keywords

  • Analog-mixed-signal (AMS) computing
  • SRAM
  • capacitive coupling
  • in-memory computing (IMC)
  • machine learning accelerator
  • neural network

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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