Bypass aware instruction scheduling for register file power reduction

Sanghyun Park, Aviral Shrivastava, Nikil Dutt, Alex Nicolau, Yunheung Paek, Eugene Earlie

Research output: Chapter in Book/Report/Conference proceedingConference contribution

17 Citations (Scopus)

Abstract

Since register files suffer from some of the highest power densities within processors, designers have investigated several architectural strategies for register file power reduction, including "On Demand RF Read" where the register file is read only if the operand value is not available from the bypasses. However, we show in this paper that significant additional reductions in the register file power consumption can be obtained by scheduling instructions so that they transfer the operands via bypasses, rather than reading from the register file. Such instruction scheduling requires the compiler to be cognizant of the bypasses in the processor pipeline. In this paper, we develop several bypass aware instruction scheduling heuristics varying in time complexity, and study their effectiveness on the Intel XScale processor pipeline running MiBench benchmarks. Our experimental results show additional power consumption reductions of up to 26% and on average 12% over and above the register file power reduction achieved through existing techniques.

Original languageEnglish (US)
Title of host publicationProceedings of the ACM SIGPLAN Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES)
Pages173-181
Number of pages9
Volume2006
StatePublished - 2006
Externally publishedYes
EventLCTES 2006 - 2006 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems - Ottawa, ON, Canada
Duration: Jun 14 2006Jun 16 2006

Other

OtherLCTES 2006 - 2006 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems
CountryCanada
CityOttawa, ON
Period6/14/066/16/06

Fingerprint

Instruction Scheduling
Scheduling
Power Consumption
Electric power utilization
Pipelines
Compiler
High Power
Time Complexity
Heuristics
Benchmark
Experimental Results

Keywords

  • Architecture-sensitive Compiler
  • Bypass-sensitive
  • Forwarding Paths
  • Operation Table
  • Power Consumption
  • Processor Bypasses
  • Register File
  • Reservation Table

ASJC Scopus subject areas

  • Computational Theory and Mathematics
  • Theoretical Computer Science

Cite this

Park, S., Shrivastava, A., Dutt, N., Nicolau, A., Paek, Y., & Earlie, E. (2006). Bypass aware instruction scheduling for register file power reduction. In Proceedings of the ACM SIGPLAN Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES) (Vol. 2006, pp. 173-181)

Bypass aware instruction scheduling for register file power reduction. / Park, Sanghyun; Shrivastava, Aviral; Dutt, Nikil; Nicolau, Alex; Paek, Yunheung; Earlie, Eugene.

Proceedings of the ACM SIGPLAN Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES). Vol. 2006 2006. p. 173-181.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Park, S, Shrivastava, A, Dutt, N, Nicolau, A, Paek, Y & Earlie, E 2006, Bypass aware instruction scheduling for register file power reduction. in Proceedings of the ACM SIGPLAN Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES). vol. 2006, pp. 173-181, LCTES 2006 - 2006 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems, Ottawa, ON, Canada, 6/14/06.
Park S, Shrivastava A, Dutt N, Nicolau A, Paek Y, Earlie E. Bypass aware instruction scheduling for register file power reduction. In Proceedings of the ACM SIGPLAN Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES). Vol. 2006. 2006. p. 173-181
Park, Sanghyun ; Shrivastava, Aviral ; Dutt, Nikil ; Nicolau, Alex ; Paek, Yunheung ; Earlie, Eugene. / Bypass aware instruction scheduling for register file power reduction. Proceedings of the ACM SIGPLAN Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES). Vol. 2006 2006. pp. 173-181
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