Branch penalty reduction on IBM cell SPUs via software branch hinting

Jing Lu, Yooseong Kim, Aviral Shrivastava, Chuan Huang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Scopus citations

Abstract

As power-efficiency becomes paramount concern in processor design, architectures are coming up that completely do away with hardware branch prediction, and rely solely on software branch hinting. A popular example is the Synergistic Processing Unit (SPU) in the IBM Cell processor. To be able to minimize the branch penalty using branch hint instructions, in addition to estimating the branch probabilities (which has been looked at before [6, 25, 24]), it is important to carefully insert branch hints. Towards this, in this paper, we i) construct a branch penalty model for compiler, ii) formulate the problem of minimizing branch penalty using branch hinting and iii) propose a heuristic to solve this problem. The heuristic is based on three basic techniques that we introduce in this paper: NOP padding, hint pipelining, and nested loop restructuring. Experimental results on several benchmarks show that our solution can reduce the branch penalty as much as 35.4% over the previous approach.

Original languageEnglish (US)
Title of host publicationEmbedded Systems Week 2011, ESWEEK 2011 - Proceedings of the 9th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS'11
Pages355-364
Number of pages10
DOIs
StatePublished - Nov 22 2011
EventEmbedded Systems Week 2011, ESWEEK 2011 - 9th IEEE/ACM International Conference on Hardware/Software-Codesign and System Synthesis, CODES+ISSS'11 - Taipei, Taiwan, Province of China
Duration: Oct 9 2011Oct 14 2011

Publication series

NameEmbedded Systems Week 2011, ESWEEK 2011 - Proceedings of the 9th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS'11

Other

OtherEmbedded Systems Week 2011, ESWEEK 2011 - 9th IEEE/ACM International Conference on Hardware/Software-Codesign and System Synthesis, CODES+ISSS'11
CountryTaiwan, Province of China
CityTaipei
Period10/9/1110/14/11

Keywords

  • Branch hint
  • Cell processor
  • Compiler optimization

ASJC Scopus subject areas

  • Hardware and Architecture
  • Software
  • Control and Systems Engineering

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  • Cite this

    Lu, J., Kim, Y., Shrivastava, A., & Huang, C. (2011). Branch penalty reduction on IBM cell SPUs via software branch hinting. In Embedded Systems Week 2011, ESWEEK 2011 - Proceedings of the 9th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS'11 (pp. 355-364). (Embedded Systems Week 2011, ESWEEK 2011 - Proceedings of the 9th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS'11). https://doi.org/10.1145/2039370.2039425