TY - GEN
T1 - Branch-aware loop mapping on CGRAs
AU - Hamzeh, Mahdi
AU - Shrivastava, Aviral
AU - Vrudhula, Sarma
PY - 2014
Y1 - 2014
N2 - One of the challenges that all accelerators face, is to execute loops that have if-then-else constructs. There are three ways to accelerate loops with an if-then-else construct on a Coarse-grained reconfigurable architecture (CGRA): full predication, partial predication, and dual-issue scheme. In comparison with the other schemes, dual-issue scheme may achieve the best performance, but it requires compiler support - which does not exist. In this paper, we develop compiler techniques to map loops with conditionals on CGRA for the dual-issue scheme. Our experiments show: i) 40% of loops that can be accelerated on CGRA have conditionals, ii) The proposed dual-issue scheme enables our compiler to accelerate loops 40% faster than full predication scheme proposed in [12], and iii) Our compiler assisted dual issue scheme can exploit richer interconnects, if present.
AB - One of the challenges that all accelerators face, is to execute loops that have if-then-else constructs. There are three ways to accelerate loops with an if-then-else construct on a Coarse-grained reconfigurable architecture (CGRA): full predication, partial predication, and dual-issue scheme. In comparison with the other schemes, dual-issue scheme may achieve the best performance, but it requires compiler support - which does not exist. In this paper, we develop compiler techniques to map loops with conditionals on CGRA for the dual-issue scheme. Our experiments show: i) 40% of loops that can be accelerated on CGRA have conditionals, ii) The proposed dual-issue scheme enables our compiler to accelerate loops 40% faster than full predication scheme proposed in [12], and iii) Our compiler assisted dual issue scheme can exploit richer interconnects, if present.
KW - Coarse-Grained Reconfigurable Architectures
KW - Compilation
KW - Modulo Scheduling
UR - http://www.scopus.com/inward/record.url?scp=84903184945&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84903184945&partnerID=8YFLogxK
U2 - 10.1145/2593069.2593100
DO - 10.1145/2593069.2593100
M3 - Conference contribution
AN - SCOPUS:84903184945
SN - 9781479930173
T3 - Proceedings - Design Automation Conference
BT - DAC 2014 - 51st Design Automation Conference, Conference Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 51st Annual Design Automation Conference, DAC 2014
Y2 - 2 June 2014 through 5 June 2014
ER -