TY - GEN
T1 - Boundary element method macromodels for 2-D hierarchical capacitance extraction
AU - Aykut Dengi, E.
AU - Rohrer, Ronald A.
N1 - Funding Information:
Capacitance extraction is a critical step in submicron integrated circuit interconnect modeling. In [4] a hierarchical 2-D capacitance extraction method for VLSI circuits was introduced. The method uses a geometrical hierarchical partitioning on the 2-D vertical cross-section of a VLSI circuit. These partitions are characterized at their interfaces by macromodel capacitance matrices which can be combined to yield a global capacitance matrix for a given set of conductors or the coupling capacitance values for a given conductor (Fig. 1). A library of such macromodels, which is sufficient to describe any vertical cross section for a given technology, is built as a pre-processing step to improve runtime extraction efficiency. Irregular conductor geometries as well as conformal dielectrics are handled at the preprocessing stage, enhancing runtime efficiency without affecting accuracy. To aid understanding, [4] introduced the method in a Finite Difference Method formulation, but the method is in fact best implemented using the Boundary Element Method (BEM). The efficiency of the runtime global solution is proportional to the number of ports on each element. In the finite difference formulation, the number of ports is intimately related to the discretization used inside the element. Hence, when we discretize the conductor surfaces finely, as we should, we end up with a large number of ports. In this paper, we present the BEM formulation, which allows us to effectively decouple the discretization on the conductors and the discret-ization at the boundary (hence the number of ports), leading to a better trade-off between accuracy and efficiency. The rest of the paper is organized as follows: In Section 2, the basic BEM formulation for macromodels is presented; Section 3 t. This work was supported by the National Science Foundation under Grant MIP-9216942, and by the Semiconductor Research Corporation under Contract DC-068.
Publisher Copyright:
© 1998 ACM.
PY - 1998
Y1 - 1998
N2 - A 2-D hierarchical field solution method was recently introduced for capacitance extraction for VLSI interconnect modeling. In this paper, we present several extensions to the method including a Boundary Element Method (BEM) formulation for creating macromodels, which provides a better trade-off between accuracy and efficiency, as well as parameterized elements, which allow the analysis of gridless designs with reasonable accuracy and a small library size.
AB - A 2-D hierarchical field solution method was recently introduced for capacitance extraction for VLSI interconnect modeling. In this paper, we present several extensions to the method including a Boundary Element Method (BEM) formulation for creating macromodels, which provides a better trade-off between accuracy and efficiency, as well as parameterized elements, which allow the analysis of gridless designs with reasonable accuracy and a small library size.
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M3 - Conference contribution
AN - SCOPUS:0031635679
SN - 078034409X
T3 - Proceedings - Design Automation Conference
SP - 218
EP - 223
BT - Proceedings 1998 - Design and Automation Conference, DAC 1998
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 35th Design and Automation Conference, DAC 1998
Y2 - 15 June 1998 through 19 June 1998
ER -