@inproceedings{10a49e95b4f146a28a0e3a7d8138f8de,
title = "Boosting the accuracy of analog test coverage computation through statistical tolerance analysis",
abstract = "Increasing numbers of analog components in today's systems necessitate system level test composition methods that utilize onchip capabilities rather than solely relying on costly DFT approaches. We outline a tolerance analysis methodology for test signal propagation to be utilized in hierarchical test generation for analog circuits. A detailed justification of this proposed novel tolerance analysis methodology is undertaken by comparing our results with detailed SPICE Monte-Carlo simulation data on several combinations of analog modules. The results of our experiments confirm the high accuracy and efficiency of the proposed tolerance analysis methodology.",
keywords = "Analog circuits, Analog computers, Boosting, Circuit faults, Circuit testing, Computational efficiency, Signal analysis, Signal generators, System testing, Tolerance analysis",
author = "S. Ozev and A. Orailoglu",
year = "2002",
month = jan,
day = "1",
doi = "10.1109/VTS.2002.1011141",
language = "English (US)",
series = "Proceedings of the IEEE VLSI Test Symposium",
publisher = "IEEE Computer Society",
pages = "213--219",
booktitle = "Proceedings - 20th IEEE VLSI Test Symposium, VTS 2002",
note = "20th IEEE VLSI Test Symposium, VTS 2002 ; Conference date: 28-04-2002 Through 02-05-2002",
}