Abstract

Memory array architecture based on emerging non-volatile memory devices have been proposed for on-chip acceleration of dot-product computation in neural networks. As recent advances in machine learning have shown that precision reduction is a useful technique to reduce the computation and memory storage, it is desired to evaluate their hardware cost. In this paper, we use a circuit-level macro model, i.e. NeuroSim, to benchmark the circuit-level performance metrics, such as chip area, latency, and dynamic energy for the XNOR-RRAM and conventional 8-bit RRAM architectures. Both architectures are implemented to process the dot-product operation of a 512×512 synaptic matrix in sequential row-by-row and parallel read-out fashion separately. The simulation results are based on RRAM models and 32nm CMOS PDK, the energy-efficiency of the parallel XNOR-RRAM architecture could achieve 311 TOPS/W, showing at least ~15× and ~621× improvement compared to the parallel and sequential conventional 8-bit RRAM architectures respectively.

Original languageEnglish (US)
Title of host publication2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages378-381
Number of pages4
ISBN (Electronic)9781538682401
DOIs
StatePublished - Jan 8 2019
Event14th IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018 - Chengdu, China
Duration: Oct 26 2018Oct 30 2018

Publication series

Name2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018

Conference

Conference14th IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018
CountryChina
CityChengdu
Period10/26/1810/30/18

Fingerprint

products
Data storage equipment
TOPS (spacecraft)
chips
machine learning
Networks (circuits)
Computer hardware
Energy efficiency
Macros
Learning systems
emerging
CMOS
hardware
RRAM
Neural networks
costs
energy
matrices
Costs
simulation

Keywords

  • hardware accelerator
  • machine learning
  • neuromorphic computing
  • non-volatile memory

ASJC Scopus subject areas

  • Biomedical Engineering
  • Electrical and Electronic Engineering
  • Instrumentation

Cite this

Peng, X., & Yu, S. (2019). Benchmark of RRAM based Architectures for Dot-Product Computation. In 2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018 (pp. 378-381). [8605606] (2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/APCCAS.2018.8605606

Benchmark of RRAM based Architectures for Dot-Product Computation. / Peng, Xiaochen; Yu, Shimeng.

2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018. Institute of Electrical and Electronics Engineers Inc., 2019. p. 378-381 8605606 (2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Peng, X & Yu, S 2019, Benchmark of RRAM based Architectures for Dot-Product Computation. in 2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018., 8605606, 2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018, Institute of Electrical and Electronics Engineers Inc., pp. 378-381, 14th IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018, Chengdu, China, 10/26/18. https://doi.org/10.1109/APCCAS.2018.8605606
Peng X, Yu S. Benchmark of RRAM based Architectures for Dot-Product Computation. In 2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018. Institute of Electrical and Electronics Engineers Inc. 2019. p. 378-381. 8605606. (2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018). https://doi.org/10.1109/APCCAS.2018.8605606
Peng, Xiaochen ; Yu, Shimeng. / Benchmark of RRAM based Architectures for Dot-Product Computation. 2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018. Institute of Electrical and Electronics Engineers Inc., 2019. pp. 378-381 (2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018).
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abstract = "Memory array architecture based on emerging non-volatile memory devices have been proposed for on-chip acceleration of dot-product computation in neural networks. As recent advances in machine learning have shown that precision reduction is a useful technique to reduce the computation and memory storage, it is desired to evaluate their hardware cost. In this paper, we use a circuit-level macro model, i.e. NeuroSim, to benchmark the circuit-level performance metrics, such as chip area, latency, and dynamic energy for the XNOR-RRAM and conventional 8-bit RRAM architectures. Both architectures are implemented to process the dot-product operation of a 512×512 synaptic matrix in sequential row-by-row and parallel read-out fashion separately. The simulation results are based on RRAM models and 32nm CMOS PDK, the energy-efficiency of the parallel XNOR-RRAM architecture could achieve 311 TOPS/W, showing at least ~15× and ~621× improvement compared to the parallel and sequential conventional 8-bit RRAM architectures respectively.",
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