Behavioral model of a 1.8 V 6b CMOS flash ADC based on device parameters

M. J. Pennell, M. Hasan, David Allee, W. Xie

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Scopus citations

Abstract

A hierarchical behavioral model of a submicron 6 bit CMOS flash analog to digital converter is presented. Circuit parameters are extracted from process dependent device data using an extension of the g m/I D methodology for use in the behavioral model. In using this approach, the model will track changes in physical device geometries without the need for re-characterization. The comparator model is validated against SPICE and system level simulation results are presented for the full converter.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems
Editors Anon
PublisherIEEE
Pages1636-1639
Number of pages4
Volume3
StatePublished - 1997
Externally publishedYes
EventProceedings of the 1997 IEEE International Symposium on Circuits and Systems, ISCAS'97. Part 4 (of 4) - Hong Kong, Hong Kong
Duration: Jun 9 1997Jun 12 1997

Other

OtherProceedings of the 1997 IEEE International Symposium on Circuits and Systems, ISCAS'97. Part 4 (of 4)
CityHong Kong, Hong Kong
Period6/9/976/12/97

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

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