Abstract
A hierarchical behavioral model of a submicron 6 bit CMOS flash analog to digital converter is presented. Circuit parameters are extracted from process dependent device data using an extension of the g m/I D methodology for use in the behavioral model. In using this approach, the model will track changes in physical device geometries without the need for re-characterization. The comparator model is validated against SPICE and system level simulation results are presented for the full converter.
| Original language | English (US) |
|---|---|
| Title of host publication | Proceedings - IEEE International Symposium on Circuits and Systems |
| Editors | Anon |
| Publisher | IEEE |
| Pages | 1636-1639 |
| Number of pages | 4 |
| Volume | 3 |
| State | Published - 1997 |
| Externally published | Yes |
| Event | Proceedings of the 1997 IEEE International Symposium on Circuits and Systems, ISCAS'97. Part 4 (of 4) - Hong Kong, Hong Kong Duration: Jun 9 1997 → Jun 12 1997 |
Other
| Other | Proceedings of the 1997 IEEE International Symposium on Circuits and Systems, ISCAS'97. Part 4 (of 4) |
|---|---|
| City | Hong Kong, Hong Kong |
| Period | 6/9/97 → 6/12/97 |
ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Electronic, Optical and Magnetic Materials