B2P2: Bounds Based Procedure Placement for instruction TLB power reduction in embedded systems

Reiley Jeyapaul, Aviral Shrivastava

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

High performance embedded processors are equipped with the Translation Look-aside Buffer (TLB) which forms the key ingredient to efficient and speedy virtual memory management. The TLB though small, is frequently accessed, and therefore not only consumes significant energy, but also is one of the important thermal hot-spots in the processor. Among the many circuit and microarchitectural techniques proposed to reduce TLB power consumption, the Use-Last TLB is one very efficient technique in which power is consumed only when different pages are accessed in succession, i.e., when there is a page-switch [26]. Though the Use-Last technique is effective in reducing i-TLB power, there is scope to further improve its effectiveness by changing the relative code placement of the program. In this work, we formulate the code placement problem to minimize the page-switches in a program. We prove that this problem is NP-complete and propose an efficient Bounds Based Procedure Placement (B2P2) heuristic to efficiently reduce the program's page-switches. Our procedure placement technique delivers an average of 76% reduction in the instrucion-TLB power with negligible (< 2%) impact on performance, over and above the reduction achieved by the Use-Last TLB architecture alone.

Original languageEnglish (US)
Title of host publicationProceedings of the 13th International Workshop on Software and Compilers for Embedded Systems, SCOPES 2010
DOIs
StatePublished - Aug 6 2010
Event13th International Workshop on Software and Compilers for Embedded Systems, SCOPES 2010 - St. Goar, Germany
Duration: Jun 28 2010Jun 29 2010

Publication series

NameProceedings of the 13th International Workshop on Software and Compilers for Embedded Systems, SCOPES 2010

Other

Other13th International Workshop on Software and Compilers for Embedded Systems, SCOPES 2010
CountryGermany
CitySt. Goar
Period6/28/106/29/10

Keywords

  • Code placement
  • Compiler technique
  • Embedded processors
  • Instruction TLB
  • Memory management
  • Power

ASJC Scopus subject areas

  • Hardware and Architecture
  • Software

Fingerprint Dive into the research topics of 'B2P2: Bounds Based Procedure Placement for instruction TLB power reduction in embedded systems'. Together they form a unique fingerprint.

  • Cite this

    Jeyapaul, R., & Shrivastava, A. (2010). B2P2: Bounds Based Procedure Placement for instruction TLB power reduction in embedded systems. In Proceedings of the 13th International Workshop on Software and Compilers for Embedded Systems, SCOPES 2010 [2] (Proceedings of the 13th International Workshop on Software and Compilers for Embedded Systems, SCOPES 2010). https://doi.org/10.1145/1811212.1811215