Autonomic microprocessor execution via self-repairing arrays

Fred A. Bower, Sule Ozev, Daniel J. Sorin

Research output: Contribution to journalArticlepeer-review

3 Scopus citations

Abstract

To achieve high reliability despite hard faults that occur during operation and to achieve high yield despite defects introduced at fabrication, a microprocessor must be able to tolerate hard faults. In this paper, we present a framework for autonomic self-repair of the array structures in microprocessors (e.g., reorder buffer, instruction window, etc.). The framework consists of three aspects: 1) detecting/diagnosing the fault, 2) recovering from the resultant error, and 3) mapping out the faulty portion of the array. For each aspect, we present design options. Based on this framework, we develop two particular schemes for self-repairing array structures (SRAS). Simulation results show that one of our SRAS schemes adds some performance overhead in the fault-free case, but that both of them mask hard faults 1) with less hardware overhead cost than higher-level redundancy (e.g., IBM mainframes) and 2) without the per-error performance penalty of existing low-cost techniques that combine error detection with pipeline flushes for backward error recovery (BER). When hard faults are present in arrays, due to operational faults or fabrication defects, SRAS schemes outperform BER due to not having to frequently flush the pipeline.

Original languageEnglish (US)
Pages (from-to)297-310
Number of pages14
JournalIEEE Transactions on Dependable and Secure Computing
Volume2
Issue number4
DOIs
StatePublished - Jan 1 2005
Externally publishedYes

Keywords

  • Logic design reliability and testing
  • Microcomputers
  • Microprocessors

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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