Automatic management of Software Programmable Memories in Many-core Architectures

Aviral Shrivastava, Nikil Dutt, Jian Cai, Majid Shoushtari, Bryan Donyanavard, Hossein Tajik

Research output: Contribution to journalArticle

4 Citations (Scopus)

Abstract

Software Programmable Memories, or SPMs, are raw on-chip memories that are not implicitly managed by the processor hardware, but explicitly by software. For example, while caches fetch data from memories automatically and maintain coherence with other caches, SPMs explicitly manage data movement between memories and other SPMs through software instructions. SPMs make the design of on-chip memories simpler, more scalable, and power efficient, but also place additional burden for programming of SPM-based processors. Traditionally, SPMs have been utilised in embedded systems, especially multimedia and gaming systems, but recently research on SPM-based systems has seen increased interest as a means to solve the memory scaling challenges of many-core architectures. This study presents an overview of the state-of-the-art in SPM management techniques in many-core processors, summarises some recent research on SPM-based systems, and outlines future research directions in this field.

Original languageEnglish (US)
Pages (from-to)288-298
Number of pages11
JournalIET Computers and Digital Techniques
Volume10
Issue number6
DOIs
StatePublished - Nov 1 2016

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Data storage equipment
Embedded systems
Hardware

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Automatic management of Software Programmable Memories in Many-core Architectures. / Shrivastava, Aviral; Dutt, Nikil; Cai, Jian; Shoushtari, Majid; Donyanavard, Bryan; Tajik, Hossein.

In: IET Computers and Digital Techniques, Vol. 10, No. 6, 01.11.2016, p. 288-298.

Research output: Contribution to journalArticle

Shrivastava, Aviral ; Dutt, Nikil ; Cai, Jian ; Shoushtari, Majid ; Donyanavard, Bryan ; Tajik, Hossein. / Automatic management of Software Programmable Memories in Many-core Architectures. In: IET Computers and Digital Techniques. 2016 ; Vol. 10, No. 6. pp. 288-298.
@article{37ec3f8c262144328ef4dcd0f5e9b3bb,
title = "Automatic management of Software Programmable Memories in Many-core Architectures",
abstract = "Software Programmable Memories, or SPMs, are raw on-chip memories that are not implicitly managed by the processor hardware, but explicitly by software. For example, while caches fetch data from memories automatically and maintain coherence with other caches, SPMs explicitly manage data movement between memories and other SPMs through software instructions. SPMs make the design of on-chip memories simpler, more scalable, and power efficient, but also place additional burden for programming of SPM-based processors. Traditionally, SPMs have been utilised in embedded systems, especially multimedia and gaming systems, but recently research on SPM-based systems has seen increased interest as a means to solve the memory scaling challenges of many-core architectures. This study presents an overview of the state-of-the-art in SPM management techniques in many-core processors, summarises some recent research on SPM-based systems, and outlines future research directions in this field.",
author = "Aviral Shrivastava and Nikil Dutt and Jian Cai and Majid Shoushtari and Bryan Donyanavard and Hossein Tajik",
year = "2016",
month = "11",
day = "1",
doi = "10.1049/iet-cdt.2016.0024",
language = "English (US)",
volume = "10",
pages = "288--298",
journal = "IET Computers and Digital Techniques",
issn = "1751-8601",
publisher = "Institution of Engineering and Technology",
number = "6",

}

TY - JOUR

T1 - Automatic management of Software Programmable Memories in Many-core Architectures

AU - Shrivastava, Aviral

AU - Dutt, Nikil

AU - Cai, Jian

AU - Shoushtari, Majid

AU - Donyanavard, Bryan

AU - Tajik, Hossein

PY - 2016/11/1

Y1 - 2016/11/1

N2 - Software Programmable Memories, or SPMs, are raw on-chip memories that are not implicitly managed by the processor hardware, but explicitly by software. For example, while caches fetch data from memories automatically and maintain coherence with other caches, SPMs explicitly manage data movement between memories and other SPMs through software instructions. SPMs make the design of on-chip memories simpler, more scalable, and power efficient, but also place additional burden for programming of SPM-based processors. Traditionally, SPMs have been utilised in embedded systems, especially multimedia and gaming systems, but recently research on SPM-based systems has seen increased interest as a means to solve the memory scaling challenges of many-core architectures. This study presents an overview of the state-of-the-art in SPM management techniques in many-core processors, summarises some recent research on SPM-based systems, and outlines future research directions in this field.

AB - Software Programmable Memories, or SPMs, are raw on-chip memories that are not implicitly managed by the processor hardware, but explicitly by software. For example, while caches fetch data from memories automatically and maintain coherence with other caches, SPMs explicitly manage data movement between memories and other SPMs through software instructions. SPMs make the design of on-chip memories simpler, more scalable, and power efficient, but also place additional burden for programming of SPM-based processors. Traditionally, SPMs have been utilised in embedded systems, especially multimedia and gaming systems, but recently research on SPM-based systems has seen increased interest as a means to solve the memory scaling challenges of many-core architectures. This study presents an overview of the state-of-the-art in SPM management techniques in many-core processors, summarises some recent research on SPM-based systems, and outlines future research directions in this field.

UR - http://www.scopus.com/inward/record.url?scp=84992625161&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84992625161&partnerID=8YFLogxK

U2 - 10.1049/iet-cdt.2016.0024

DO - 10.1049/iet-cdt.2016.0024

M3 - Article

VL - 10

SP - 288

EP - 298

JO - IET Computers and Digital Techniques

JF - IET Computers and Digital Techniques

SN - 1751-8601

IS - 6

ER -