TY - JOUR
T1 - Automatic management of Software Programmable Memories in Many-core Architectures
AU - Shrivastava, Aviral
AU - Dutt, Nikil
AU - Cai, Jian
AU - Shoushtari, Majid
AU - Donyanavard, Bryan
AU - Tajik, Hossein
N1 - Funding Information:
This work was partially supported by the NSF Variability Expedition award CCF-1029783, CCF 1055094 (CAREER), and CNS 1525855, and CCF-0916652. The authors acknowledge Dr. Ke Bai, and Dr. Luis Angel D. Bathen for their contributions.
Publisher Copyright:
© The Institution of Engineering and Technology.
PY - 2016/11/1
Y1 - 2016/11/1
N2 - Software Programmable Memories, or SPMs, are raw on-chip memories that are not implicitly managed by the processor hardware, but explicitly by software. For example, while caches fetch data from memories automatically and maintain coherence with other caches, SPMs explicitly manage data movement between memories and other SPMs through software instructions. SPMs make the design of on-chip memories simpler, more scalable, and power efficient, but also place additional burden for programming of SPM-based processors. Traditionally, SPMs have been utilised in embedded systems, especially multimedia and gaming systems, but recently research on SPM-based systems has seen increased interest as a means to solve the memory scaling challenges of many-core architectures. This study presents an overview of the state-of-the-art in SPM management techniques in many-core processors, summarises some recent research on SPM-based systems, and outlines future research directions in this field.
AB - Software Programmable Memories, or SPMs, are raw on-chip memories that are not implicitly managed by the processor hardware, but explicitly by software. For example, while caches fetch data from memories automatically and maintain coherence with other caches, SPMs explicitly manage data movement between memories and other SPMs through software instructions. SPMs make the design of on-chip memories simpler, more scalable, and power efficient, but also place additional burden for programming of SPM-based processors. Traditionally, SPMs have been utilised in embedded systems, especially multimedia and gaming systems, but recently research on SPM-based systems has seen increased interest as a means to solve the memory scaling challenges of many-core architectures. This study presents an overview of the state-of-the-art in SPM management techniques in many-core processors, summarises some recent research on SPM-based systems, and outlines future research directions in this field.
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U2 - 10.1049/iet-cdt.2016.0024
DO - 10.1049/iet-cdt.2016.0024
M3 - Article
AN - SCOPUS:84992625161
SN - 1751-8601
VL - 10
SP - 288
EP - 298
JO - IET Computers and Digital Techniques
JF - IET Computers and Digital Techniques
IS - 6
ER -