Automatic design space exploration of register bypasses in embedded processors

Register Bypassing is a popular and powerful architectural feature to improve processor performance in pipelined processors by eliminating certain data hazards. However, extensive bypassing comes with a significant impact on cycle time, area and power consumption of the processor. Recent research therefore advocates the use of partial bypassing in processor. However, accurate performance evaluation of partially bypassed processors is still a challenge; primarily due to the lack of bypass-sensitive retargetable compilation techniques. No existing partial bypass exploration framework estimates the power and area overhead of partial bypassing. As a result the designers end up making sub-optimal design decisions during the exploration of partial bypass design space. This article presents FBExplore: An automatic design space exploration framework for register bypasses. PBExplore accurately evaluates the performance of a partially bypassed processor using a bypass-sensitive compilation technique. It synthesizes the bypass control logic and estimates the area and energy overhead of each bypass configuration. PBExplore is thus able to effectively perform multi-dimensional exploration of the partial bypass design space. We present experimental results of benchmarks from the MiBench suite on the Intel XScale architecture on and demonstrate the need, utility and exploration capabilities of PBExplore.