Automatic design of binary and multiple-valued logic gates on RTD series

Krzysztof S. Berezowski, Sarma B.K. Vrudhula

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Scopus citations

Abstract

In this paper, we contribute to the binary and multiple-valued applications of resonant tunneling devices (RTDs). We propose a method of systematic design of physical parameters of RTD based logic. From the abstraction of their behavior, we model the design space as a handful of systems of linear inequalities generated for a given circuit topology and an arbitrary logic function. Any valid solution reflects the physical parameters assignment that implements the function given. We solve these systems using off-the-shelf optimization tool and verify the results using SystemC basedRTD circuit model. Our simulations confirm, that the numerical solutions are valid parameter assignments.

Original languageEnglish (US)
Title of host publicationProceedings - Thirteenth International Symposium on Temporal Representation and Reasoning, TIME 2006
Pages139-142
Number of pages4
DOIs
StatePublished - Dec 1 2005
Externally publishedYes
EventDSD'2005: 8th Euromicro Conference on Digital System Design - Porto, Portugal
Duration: Aug 30 2005Sep 3 2005

Publication series

NameProceedings - DSD'2005: 8th Euromicro Conference on Digital System Design - Architectures, Methods and Tools
Volume2005

Other

OtherDSD'2005: 8th Euromicro Conference on Digital System Design
CountryPortugal
CityPorto
Period8/30/059/3/05

ASJC Scopus subject areas

  • Engineering(all)

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