Automatic code parallelization and optimization

Research output: Chapter in Book/Report/Conference proceedingChapter

Abstract

Over the past decade, parallel processing has become increasingly prevalent. Desktop processors are manufactured with multiple cores (Intel), and commodity cluster systems have become commonplace. The IBM Cell Broadband Engine architecture contains eight processors for computation and one general-purpose processor (IBM). The trend toward multicore processors, or multiple processing elements on a single chip, is growing as more hardware companies, research laboratories, and government organizations are investing in multicore processor development. As an example, in February 2007 Intel announced a prototype for an 80-core architecture (Markoff 2007). The motivation for these emerging processor architectures is that data sizes that need to be processed in industry, academia, and government are steadily increasing (Simon 2006). Consequently, with increasing data sizes, throughput requirements for real-time processing are increasing at similar rates. As radars move from analog to wideband digital arrays and image processing systems move toward gigapixel cameras, the need to process more data at a faster rate becomes particularly vital for the high performance embedded computing community.

Original languageEnglish (US)
Title of host publicationHigh Performance Embedded Computing Handbook
Subtitle of host publicationA Systems Perspective
PublisherCRC Press
Pages381-393
Number of pages13
ISBN (Electronic)9781420006667
ISBN (Print)9780849371974
StatePublished - Jan 1 2008
Externally publishedYes

ASJC Scopus subject areas

  • Engineering(all)

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