Automated techniques for synthesis of application-specific network-on-chip architectures

Karam S. Chatha, Krishnan Srinivasan, Goran Konjevod

Research output: Contribution to journalArticle

24 Scopus citations

Abstract

This paper addresses the automated synthesis of a custom network-on-chip architecture whose topology is optimized for the specific communication requirements of the target device. The optimization objectives include power consumption and resource usage. This paper presents a two-stage synthesis approach consisting of the following: 1) core to router mapping and 2) custom topology and route generation. In particular, it presents an optimal technique for core to router mapping [stage 1)] and a factor-2 approximation algorithm for custom topology generation [stage 2)]. The superior quality of the techniques is established by experimentation with benchmark applications and by comparisons with existing approaches.

Original languageEnglish (US)
Article number4527105
Pages (from-to)1425-1438
Number of pages14
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume27
Issue number8
DOIs
StatePublished - Aug 1 2008

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Keywords

  • Application specific integrated circuit (ASIC)
  • Approximation methods
  • Design automation
  • Network-on-chip

ASJC Scopus subject areas

  • Software
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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