Abstract
Many embedded SoC architectures require minimal on-chip communication latency and jitter. Further, each communication transaction is expected to display some jitter in its start time due to dynamic events. The paper presents a novel synthesis technique that generates an optimized NoC architecture composed of best effort traffic class routers. The technique minimizes both the average packet latency and jitter in the presence of transaction initiation jitter. In comparison to an existing approach the designs generated by our technique demonstrated 41% reduction in average latency, 39% reduction in standard deviation of latency, identical power consumption and 24% increase in router resources.
| Original language | English (US) |
|---|---|
| Title of host publication | Embedded Systems Week 2009 - 7th IEEE/ACM International Conference on Hardware/Software-Co-Design and System Synthesis, CODES+ISSS 2009 |
| Pages | 471-480 |
| Number of pages | 10 |
| DOIs | |
| State | Published - 2009 |
| Event | Embedded Systems Week 2009, ESWEEK 2009 - 7th IEEE/ACM International Conference on Hardware/Software-Co-Design and System Synthesis, CODES+ISSS 2009 - Grenoble, France Duration: Oct 11 2009 → Oct 16 2009 |
Other
| Other | Embedded Systems Week 2009, ESWEEK 2009 - 7th IEEE/ACM International Conference on Hardware/Software-Co-Design and System Synthesis, CODES+ISSS 2009 |
|---|---|
| Country | France |
| City | Grenoble |
| Period | 10/11/09 → 10/16/09 |
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Keywords
- Best-effort communication
- Latency
- Network-on-chip
- Synthesis
ASJC Scopus subject areas
- Hardware and Architecture
- Software
Cite this
Automated technique for design of NoC with minimal communication latency. / Leary, Glenn; Chatha, Karam S.
Embedded Systems Week 2009 - 7th IEEE/ACM International Conference on Hardware/Software-Co-Design and System Synthesis, CODES+ISSS 2009. 2009. p. 471-480.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - Automated technique for design of NoC with minimal communication latency
AU - Leary, Glenn
AU - Chatha, Karam S.
PY - 2009
Y1 - 2009
N2 - Many embedded SoC architectures require minimal on-chip communication latency and jitter. Further, each communication transaction is expected to display some jitter in its start time due to dynamic events. The paper presents a novel synthesis technique that generates an optimized NoC architecture composed of best effort traffic class routers. The technique minimizes both the average packet latency and jitter in the presence of transaction initiation jitter. In comparison to an existing approach the designs generated by our technique demonstrated 41% reduction in average latency, 39% reduction in standard deviation of latency, identical power consumption and 24% increase in router resources.
AB - Many embedded SoC architectures require minimal on-chip communication latency and jitter. Further, each communication transaction is expected to display some jitter in its start time due to dynamic events. The paper presents a novel synthesis technique that generates an optimized NoC architecture composed of best effort traffic class routers. The technique minimizes both the average packet latency and jitter in the presence of transaction initiation jitter. In comparison to an existing approach the designs generated by our technique demonstrated 41% reduction in average latency, 39% reduction in standard deviation of latency, identical power consumption and 24% increase in router resources.
KW - Best-effort communication
KW - Latency
KW - Network-on-chip
KW - Synthesis
UR - http://www.scopus.com/inward/record.url?scp=72149095107&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=72149095107&partnerID=8YFLogxK
U2 - 10.1145/1629435.1629499
DO - 10.1145/1629435.1629499
M3 - Conference contribution
AN - SCOPUS:72149095107
SN - 9781605586281
SP - 471
EP - 480
BT - Embedded Systems Week 2009 - 7th IEEE/ACM International Conference on Hardware/Software-Co-Design and System Synthesis, CODES+ISSS 2009
ER -