Automated technique for design of NoC with minimal communication latency

Glenn Leary, Karam S. Chatha

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Citations (Scopus)

Abstract

Many embedded SoC architectures require minimal on-chip communication latency and jitter. Further, each communication transaction is expected to display some jitter in its start time due to dynamic events. The paper presents a novel synthesis technique that generates an optimized NoC architecture composed of best effort traffic class routers. The technique minimizes both the average packet latency and jitter in the presence of transaction initiation jitter. In comparison to an existing approach the designs generated by our technique demonstrated 41% reduction in average latency, 39% reduction in standard deviation of latency, identical power consumption and 24% increase in router resources.

Original languageEnglish (US)
Title of host publicationEmbedded Systems Week 2009 - 7th IEEE/ACM International Conference on Hardware/Software-Co-Design and System Synthesis, CODES+ISSS 2009
Pages471-480
Number of pages10
DOIs
StatePublished - 2009
EventEmbedded Systems Week 2009, ESWEEK 2009 - 7th IEEE/ACM International Conference on Hardware/Software-Co-Design and System Synthesis, CODES+ISSS 2009 - Grenoble, France
Duration: Oct 11 2009Oct 16 2009

Other

OtherEmbedded Systems Week 2009, ESWEEK 2009 - 7th IEEE/ACM International Conference on Hardware/Software-Co-Design and System Synthesis, CODES+ISSS 2009
CountryFrance
CityGrenoble
Period10/11/0910/16/09

Fingerprint

Jitter
Communication
Routers
Electric power utilization
Network-on-chip

Keywords

  • Best-effort communication
  • Latency
  • Network-on-chip
  • Synthesis

ASJC Scopus subject areas

  • Hardware and Architecture
  • Software

Cite this

Leary, G., & Chatha, K. S. (2009). Automated technique for design of NoC with minimal communication latency. In Embedded Systems Week 2009 - 7th IEEE/ACM International Conference on Hardware/Software-Co-Design and System Synthesis, CODES+ISSS 2009 (pp. 471-480) https://doi.org/10.1145/1629435.1629499

Automated technique for design of NoC with minimal communication latency. / Leary, Glenn; Chatha, Karam S.

Embedded Systems Week 2009 - 7th IEEE/ACM International Conference on Hardware/Software-Co-Design and System Synthesis, CODES+ISSS 2009. 2009. p. 471-480.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Leary, G & Chatha, KS 2009, Automated technique for design of NoC with minimal communication latency. in Embedded Systems Week 2009 - 7th IEEE/ACM International Conference on Hardware/Software-Co-Design and System Synthesis, CODES+ISSS 2009. pp. 471-480, Embedded Systems Week 2009, ESWEEK 2009 - 7th IEEE/ACM International Conference on Hardware/Software-Co-Design and System Synthesis, CODES+ISSS 2009, Grenoble, France, 10/11/09. https://doi.org/10.1145/1629435.1629499
Leary G, Chatha KS. Automated technique for design of NoC with minimal communication latency. In Embedded Systems Week 2009 - 7th IEEE/ACM International Conference on Hardware/Software-Co-Design and System Synthesis, CODES+ISSS 2009. 2009. p. 471-480 https://doi.org/10.1145/1629435.1629499
Leary, Glenn ; Chatha, Karam S. / Automated technique for design of NoC with minimal communication latency. Embedded Systems Week 2009 - 7th IEEE/ACM International Conference on Hardware/Software-Co-Design and System Synthesis, CODES+ISSS 2009. 2009. pp. 471-480
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