Abstract
While in the digital domain, test development is primarily conducted with the use of automated tools, knowledge-based, ad hoc test methods have been in use in the analog domain. High levels of design integration and increasing complexity of analog blocks within a system necessitate automated system-level analog test development tools. We outline a methodology for specification-based automated test generation and fault simulation for analog circuits. Test generation is targeted at providing the highest coverage for each specified parameter. The flexibility of assigning analog test attributes is utilized for merging tests leading to test time reduction with no loss in test coverage. Further optimization in test time is obtained through fault simulations by selecting tests that provide adequate coverage in terms of several components and dropping the ones that do not provide additional coverage. A system-level test set target in the given set of specifications, along with fault and yield coverages in terms of each targeted parameter, and testability problems are determined through the proposed methodology.
Original language | English (US) |
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Pages (from-to) | 169-178 |
Number of pages | 10 |
Journal | Analog Integrated Circuits and Signal Processing |
Volume | 35 |
Issue number | 2-3 |
DOIs | |
State | Published - May 1 2003 |
Externally published | Yes |
Keywords
- Analog test
- High-level modeling
- Para metric test
- Test coverage
ASJC Scopus subject areas
- Signal Processing
- Hardware and Architecture
- Surfaces, Coatings and Films