Asynchronous VLSI architecture for adaptive echo cancellation

R. P. Mackey; J. J. Rodríguez; J. D. Carothers; S. B.K. Vrudhula

doi:10.1049/el:19960509

Asynchronous VLSI architecture for adaptive echo cancellation

R. P. Mackey, J. J. Rodríguez, J. D. Carothers, S. B.K. Vrudhula

Engineering, Ira A. Fulton Schools of (IAFSE)

Research output: Contribution to journal › Article › peer-review

1 Scopus citations

Abstract

A single chip, 128 coefficient, asynchronous echo canceller is presented. Cancellation is performed by an FIR filter whose coefficients are adapted using the power-of-two modified LMS algorithm. The pipelined circuit updates all coefficients and generates the filtered output every cycle while allowing a sampling rate >206.5kHz.

Original language	English (US)
Pages (from-to)	710-711
Number of pages	2
Journal	Electronics Letters
Volume	32
Issue number	8
DOIs	https://doi.org/10.1049/el:19960509
State	Published - Apr 11 1996

Keywords

Adaptive systems
Echo suppression
VLSI

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1049/el:19960509

Cite this

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title = "Asynchronous VLSI architecture for adaptive echo cancellation",

abstract = "A single chip, 128 coefficient, asynchronous echo canceller is presented. Cancellation is performed by an FIR filter whose coefficients are adapted using the power-of-two modified LMS algorithm. The pipelined circuit updates all coefficients and generates the filtered output every cycle while allowing a sampling rate >206.5kHz.",

keywords = "Adaptive systems, Echo suppression, VLSI",

author = "Mackey, {R. P.} and Rodr{\'i}guez, {J. J.} and Carothers, {J. D.} and Vrudhula, {S. B.K.}",

year = "1996",

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AU - Rodríguez, J. J.

AU - Carothers, J. D.

AU - Vrudhula, S. B.K.

PY - 1996/4/11

Y1 - 1996/4/11

N2 - A single chip, 128 coefficient, asynchronous echo canceller is presented. Cancellation is performed by an FIR filter whose coefficients are adapted using the power-of-two modified LMS algorithm. The pipelined circuit updates all coefficients and generates the filtered output every cycle while allowing a sampling rate >206.5kHz.

AB - A single chip, 128 coefficient, asynchronous echo canceller is presented. Cancellation is performed by an FIR filter whose coefficients are adapted using the power-of-two modified LMS algorithm. The pipelined circuit updates all coefficients and generates the filtered output every cycle while allowing a sampling rate >206.5kHz.

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KW - Echo suppression

KW - VLSI

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Asynchronous VLSI architecture for adaptive echo cancellation

Abstract

Keywords

ASJC Scopus subject areas

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