Asynchronous VLSI architecture for adaptive echo cancellation

R. P. Mackey, J. J. Rodríguez, J. D. Carothers, S. B.K. Vrudhula

Research output: Contribution to journalArticle

Abstract

A single chip, 128 coefficient, asynchronous echo canceller is presented. Cancellation is performed by an FIR filter whose coefficients are adapted using the power-of-two modified LMS algorithm. The pipelined circuit updates all coefficients and generates the filtered output every cycle while allowing a sampling rate >206.5kHz.

Original languageEnglish (US)
Pages (from-to)710-711
Number of pages2
JournalElectronics Letters
Volume32
Issue number8
DOIs
StatePublished - Apr 11 1996
Externally publishedYes

Keywords

  • Adaptive systems
  • Echo suppression
  • VLSI

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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