ASSOCIATIVE PROCESSOR ARCHITECTURE - A SURVEY.

Sik-Sang Yau, H. S. Fung

Research output: Contribution to journalArticle

48 Citations (Scopus)

Abstract

A survey of the architecture of various associative processors is presented with emphasis on their characteristics, categorization, and implementation, and especially on recent developments. Based on their architecture, associative processors are classified into four categories, namely fully parallel, bit-serial, word-serial and block-oriented. The fully parallel associative processors are divided into two classes, word-organized and distributed logic associative processors.

Original languageEnglish (US)
Pages (from-to)3-27
Number of pages25
JournalACM Computing Surveys
Volume9
Issue number1
DOIs
StatePublished - Mar 1977
Externally publishedYes

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Categorization
Logic
Architecture
Class

ASJC Scopus subject areas

  • Computational Theory and Mathematics
  • Theoretical Computer Science

Cite this

ASSOCIATIVE PROCESSOR ARCHITECTURE - A SURVEY. / Yau, Sik-Sang; Fung, H. S.

In: ACM Computing Surveys, Vol. 9, No. 1, 03.1977, p. 3-27.

Research output: Contribution to journalArticle

Yau, Sik-Sang ; Fung, H. S. / ASSOCIATIVE PROCESSOR ARCHITECTURE - A SURVEY. In: ACM Computing Surveys. 1977 ; Vol. 9, No. 1. pp. 3-27.
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